Intel Corporation

Roshan J Fernando

Keng L Wong

Robert F Krick

Jeffrey E Smith

Gregory F Taylor

Alan Beecher Kyker

Douglas M Carmean

Martin Spence Denham

Chan W Lee

Amar A Ghori

Adalberto Golbert

Kathakali Debnath

Anurag Sah

Douglas M Carean

Vihang D Pandya

Milind Mittal

Yoav Hochberg

Self modifying code is detected using a translation lookaside buffer in order to provide cache coherency. The translation lookaside buffer has physical page addresses stored therein over which snoops can be performed using the physical memory address of a store into memory. The translation lookaside buffer includes a content addressable memory which not only provides page translation but provides content addressability based on the physical page addresses stored therein. If a match occurs during a snoop using the translation lookaside buffer, it is possible that an SMC occurred within the page of locations stored in memory associated with the matched physical page addresses. To provide finer granularity than a page of addresses, FINE HIT bits are included with each entry in the cache associating information in the cache to portions of a page within memory. Snoop logic performs the comparison of the FINE HIT bits with the respective lower order bits of the physical address to determine if a self modifying code condition has occurred within the portion of memory that may be stored in the cache.

Method and apparatus for self modifying code detection using a translation lookaside buffer

A computer system is disclosed having a processor with a type input pin that indicates whether the processor is coupled as an OEM processor a single processor or a dual processor computer system or as an upgrade processor in the dual processor computer system. The processor includes an upgrade/OEM output pin coupled to transfer an upgrade/OEM signal over a system bus if the type input pin indicates the OEM processor. The upgrade/OEM signal indicates whether the OEM processor or the upgrade processor is a bus owner of the system bus.

Processor that indicates system bus ownership in an upgradable

A method and apparatus for reducing contention in an integrated circuit during power-up. According to one aspect of the invention, an initialization circuit is included in an integrated circuit. In response to receiving Vcc, the initialization circuit generates a substitute clock signal and a substitute reset signal. The substitute clock signal and substitute reset signal are substituted for an off chip generated clock signal and an off chip generated reset signal during power-up until a predetermined condition is met. In response to receiving the substitute clock signal and the substitute reset signal, a plurality of circuits on said integrated circuit are initialized.

Power-on initializing circuit

An apparatus and a method for embedding a dynamic state machine in a static integrated circuit environment. A static integrated circuit environment which is capable of suspending operation during a power down clock-stopped condition and resuming operation from a stored state at the conclusion of the power down condition is combined with a dynamic state machine featuring dynamic latches embedded in the static integrated circuit environment. The disclosed dynamic state machine is also configured to suspend operation during the power down condition and resume operation after the power down condition from the stored stated. In addition, both the static integrated circuit environment and the embedded dynamic state machine draw minimal power during the power down condition. With the dynamic state machine embedded in the static integrated circuit environment of the present invention, faster overall circuit operation is realized with less clock capacitance, with less integrated circuit area utilized as well as reduced power consumption.

Apparatus and a method for embedding dynamic state machines in a static

A micro processor including a bus fraction register with an encoding which when decoded indicates either a bus fraction encoding or a stop clock function, data processing logic that includes a number of units including a bus unit, arranged as an instruction pipeline. The units are clocked by an internal clock running at a first frequency and operating with an I/O bus clocked by an I/O clock running at a second frequency which is a fraction of the first frequency. A stop clock signal is generated upon the condition that the bus fraction register contains the stop clock encoding. A bus unit busy (BBSY) signal line is polled to ensure that all pending bus cycles in the pipeline are completed, the polling being initiated in response to the stop clock signal. A special cycle encoded to indicate the stop clock function is run to inform the units of the microprocessor that the internal and I/O clocks are going to stop toggling. The internal and I/O clocks are signaled to stop in response to a NOP micro instruction placed in the pipe line, that indicates that the pipeline is clear of pending instructions. A number of NOPs are executed, the number being determined by the amount of time required by the I/O clock to stop.

System for loading PLL from bus fraction register when bus fraction

A flip-flop circuit is described. The flip-flop circuit receives the data signal from a data input, receives a trigger signal from a trigger input, generates a pulse signal in response to an edge in the trigger signal, and stores the data signal in response to the pulse. Alternatively, the flip-flop circuit receives a data signal through a data input, receives a trigger signal through a trigger input, stores the data signal in a latch, and suppresses the trigger signal to the latch when the data signal stored in the latch corresponds to the data signal received through the data input.

Pulsed flip-flop circuit

A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The computer system is provided with an upgrade socket for receiving the second processing unit, as well as a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system. Therefore, an inexpensive method and apparatus are provided for greatly enhancing the speed of a uniprocessing system to that of a multiprocessing system without the cost traditionally associated with multiprocessing systems.

Method and apparatus for operating a single CPU computer system as a

Apparatus for enabling internal data processing logic including a number of units clocked at a first frequency to operate with an external bus operating at a second frequency that is a fraction m/n of said first frequency. A first bus is connected via readers to data latched for data transfer from the number internal units of the data processing logic to the data latches. A second bus is connected via drivers to the data latches for data transfer from internal bus units to the data latches. The data latches are connected to the external bus. A control circuit connected to the readers and drivers controls the readers and drivers to guarantee that sampling is done when logic is stable. The control circuit includes priority logic for determining priority between the units for permitting a high priority unit to transfer data on the external bus. Upon the condition that m=1 and n is any positive integer, transfer of data from the external bus to the first bus occurs at the point in time that the internal clock and the external clock are aligned. Upon the condition that m=2 and n is any positive odd integer, transfer of data from the external bus to the second bus occurs at the point in time that the internal clock and the external clock are aligned. The priority logic prevents enabling the drivers during any period during which the internal clock and the external clock are not aligned.

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Portland, OR, United States of America

Roshan J Fernando