Analog Devices,inc.

Rosamaria Croughwell

Marc E Goldfarb

Peter John Katzin

A frequency detection system for producing clock pulses having a frequency equal to the frequency of a stream of binary data. The system includes a voltage controlled oscillator for producing the clock pulses. The frequency of such clock pulses changes in accordance with a control signal. Each one of the clock pulses has four sequential, one-quarter period phases. Adjacent phases are separated by boundaries to divide each clock pulse period into four quadrants. A frequency detector is fed by detected edges of the stream of binary data and the clock pulses for producing the control signal in accordance with the difference in frequency between the frequency of the clock pulses and the frequency of the stream of binary data. A lock-out circuit prevents subsequent production of the control signal until a subsequently detected data edge crosses a different one of the boundaries.

Frequency detector

A variable gain amplifier has at least two branches connected in parallel to drive a common output load. Each branch includes at least two FETs in a cascode configuration. A first FET in each branch is arranged to receive an input signal and to amplify the signal in a common source configuration; the second FET is arranged in a common gate configuration with its source receiving the output current of the first FET. The gate of the second FET is coupled to a corresponding gain control input so that the second FET is enabled when the gate receives an enabling gain control signal and disabled otherwise. Preferably the first and second FETs in each branch are biased in a saturation region of operation when the second FET is enabled by the gain control input. This maintains a low distortion figure throughout the dynamic range of the gain control. Preferably, the invention also includes an active fixed gain power amplification stage for coupling the output to a power amplifier.

Stepped gain controlled RF driver amplifier in CMOS

An improved charge pump circuit includes a charge pump capacitor having first and second terminals for charging in first and second polarities; a current source device for supplying current selectively to the charge pump capacitor through the first and second terminals; a clamping device for defining first and second clamping voltages for the first and second terminals, respectively; a switching device for selectively connecting the current source device to one of the terminals and connecting the clamping device to the other of the terminals; and a clamp control device, responsive to the differential mode voltage across the charge pump capacitor, for setting the clamping voltages to obtain a difference between the clamping voltages equal to said differential mode voltage and pumping equal charge into the charge pump capacitor in either polarity.

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Methuen, MA, United States of America

Rosamaria Croughwell