International Business Machines Corporation

Rory D Loughran

Joseph Natonio

Charles S Chiu

Gulsun Yasar

Robert A Proctor

James Patrick Libous

A method of analyzing I/O cell layouts for integrated circuits, such as ASICs, includes defining a proposed I/O cell layout on a selected chip image, providing a set of limit rules for electromigration, IR voltage drop and di/dt noise for the selected chip image, providing characteristics for each I/O cell type used in the proposed I/O cell layout, checking the proposed I/O cell layout by applying the limit rules to the proposed I/O cell layout and reporting all I/O cells used in the proposed I/O cell layout that do not meet the limit rules for the selected chip image.

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Richmond, VT, United States of America

Rory D Loughran