International Business Machines Corporation

Rory D Jackson

Dong Chen

Paul William Coteus

Alan G Gara

Gerard Vincent Kopcsay

Wayne Melvin Barrett

Ben Jesse Nathanson

Todd Edward Takken

Pavlos Michael Vranas

Yarsun Hsu

Vern A Norton

William C Brantley, Jr

Wayne S Groh

Paylos Michael Vranas

Arthur Joseph Hoane, Jr

Willi K Rackl

A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.

Data capture technique for high speed signaling

A parallel processing computer having a three dimensional (3D) torus topology. The computer includes multiple nodes formed in rows, multiple leap frog connections, and multiple end connections. The rows extend into the X, Y, and Z dimensions. The 3D torus topology of the present invention is achieved as follows. Along every row, end nodes are connected to adjacent nodes by the end connections. Also, along every row, alternate nodes are connected by the leap frog connections. Thus, the use of the leap frog connections results in an alternating connection pattern among the nodes.

Modular and infinitely extendable three dimensional torus packaging

A switch queue structure for one-network parallel processor systems minimizes chip count and reduces the possibility of deadlock which might otherwise occur with this type of switch structure. The switch queue structure comprises a plurality of input ports and a plurality of output ports equal in number to a number of processor/memory elements (PMEs) in a parallel processor system. A plurality of identical stages interconnect the plurality of input ports and the plurality of output ports. Each stage includes a plurality of first groups of first-in, first-out (FIFO) registers storing request messages, a plurality of second groups of first-in, first-out registers storing response messages, and a plurality of multiplexers. Each of the multiplexers have inputs connected to the FIFO registers in each of the first and second groups for routing responses to memory requests from addressed processor/memory elements to requesting processor/memory elements and for routing memory requests from processor/memory elements to addressed processor/memory elements.

Switch queue structure for one-network parallel processor systems

Packet switch protocol and circuitry for implementing it are disclosed. According to this protocol, a message transmitter of a first node in the network may send data through a data transmission link at a predetermined rate until it is signalled, via a control signal generated by a message receiver in a second node, to suspend its transmissions. The message transmitter may also be signalled to resume transmitting data. The message receiver includes a buffer memory in which messages are temporarily stored if their selected path is blocked as they pass through the network. When the amount of available space in the buffer is less than a preprogrammed threshold value, the message receiver generates the control signal to suspend message transmission. This threshold value leaves sufficient space in the buffer to store any data which may be in the pipeline between the transmitter and the receiver. When the amount of available space rises above this threshold, the message receiver indicates to the transmitter to resume transmission. A message spanning an interface during transmission may be suspended without losing spatial contiguousness. The message transmitter also transmits a signal which marks the last portion of a message. This signal is stored in the buffer with the message data and is used to delimit messages in the buffer, allowing multiple messages to be stored in one buffer without extra delimiting values.

System for implementing to a packet switch protocol for a multinode data

When a data stream includes long sections of data that are repeated periodically, storage space may be saved by not including full repetitions of such sections in the storage. However, when the data is to be read from storage for utilization, the omitted repetitious sections must be inserted. This is accomplished by providing hardware apparatus which recognizes a particular flag occurring in the stored data. After recognizing the flag, the expansion apparatus interprets the next piece of information in the data stream as being the storage address of the start of a section of data that is to be inserted into the data stream; the next piece of information is interpreted as being the length of the section of data to be inserted; and the next following piece of information is the number of times that the section of data is to be inserted. The apparatus will respond to the flag and its associated indicators by inserting the appropriate data section the indicated number of times.

Data expansion apparatus

Growing community of inventors

Eastchester, NY, United States of America

Rory D Jackson