International Business Machines Corporation

Roopesh Ambalath Matayambath

Carsten Greiner

Juergen M Ruf

Dirk Allmendinger

Joerg Kayser

Paul Allen Ganfield

Clinton E Bubb

Ralf Winkelmann

Chaitanya Kancherla

Sven Boekholt

Testing a packet sequence number checker. The packet sequence number checker may check a packet-based data communication between two interconnected devices. An error injector may be provided in-between the interconnected devices such that the data packets may be received from one of the two interconnected devices and may be sent to the other one of the two interconnected devices by the error injector. A received packet is randomly selected from a packet data stream between the two interconnected devices and stored in a buffer. A length of a later received data packet from the same sender of the two interconnected devices is compared with the selected buffered data packet, and the later received data packet is replaced by the selected buffered data packet.

Injecting lost packets and protocol errors in a simulation environment

A method, data processing system, and computer program product for verifying the functionality of a digital circuit. The method includes transmitting sequences of parallel data packets via parallel data transfer paths. Prior to receipt of at least two of the transmitted sequences, a first skew is introduced between the at least two of the transmitted sequences. This introduction includes inserting one or more parallel control data packets in the transmitted sequences, and erasing one of the control data packets, replacing one of the control data packets, and inserting another control data packet in one of the sequences. The method includes determining if an expected indicator signal is provided in the form of an overflow indicator or an underflow indicator.

Method for verifying the functionality of a digital circuit

A computer program product and computer system for analyzing code to improve efficiency of simulating a hardware system. A computer identifies one or more functions calling an application programming interface of a hardware simulator simulating the hardware system. In response to determining that left hand sides of respective one or more Boolean expressions are associated with the one or more functions calling the application programming interface and right hand sides are not associated with the one or more functions calling the application programming interface, the computer identifies the respective one or more Boolean expressions as one or more improvement points in source code for verifying a hardware model of the hardware system.

Code analysis for simulation efficiency improvement

A method, computer program product, and computer system for analyzing code to improve efficiency of simulating a hardware system. A computer identifies one or more functions calling an application programming interface of a hardware simulator simulating the hardware system. In response to determining that left hand sides of respective one or more Boolean expressions are associated with the one or more functions calling the application programming interface and right hand sides are not associated with the one or more functions calling the application programming interface, the computer identifies the respective one or more Boolean expressions as one or more improvement points in source code for verifying a hardware model of the hardware system.

A mechanism for verifying order of entities being processed by a device under test (DUT) is provided. The mechanism includes arranging the entities into a temporal order, and encoding the entities to maintain the temporal order of the entities and produce encoded entities with each being a random value. The encoded entities each have a one-to-one mapping to their corresponding one of the entities in the temporal order. The encoded entities are input into the DUT to verify its output, and responsive to detecting an error in the output corresponding to one encoded entity, the one encoded entity is decoded into a current decoded error entity. It is determined which is lower in the temporal order between the current decoded error entity and a previous decoded error entity. Responsive to the current decoded error entity being lower than the previous decoded error entity, the current decoded error entity is stored.

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Bengaluru, India

Roopesh Ambalath Matayambath