Intel Corporation

Rony Ghattas

Christopher P Mozak

Theodore Zale Schoenborn

Tsvika Kurts

Zvika Greenfield

Bruce Querbach

David G Ellis

Todd M Witter

Bryan L Spry

Jay Joseph Nejedlo

Marcelo Yuffe

Philip Abraham

Christopher E Yunker

Jayasekhar Tholiyil

Sean T Baartmans

Marcus R Winston

Arie Bernstein

Eilon Hazan

Charles D Lucas

A processing device comprises a debug port controller to monitor operations of the processing device to determine whether the processing device is operating in a first mode or a second mode and to collect trace information comprising operating characteristics of the processing device. The processing device further comprises a display engine logic to process display data for output to a display device. In addition, the processing device comprises a display engine interface to provide, to a plurality of existing platform connectors, the display data from the display engine logic when the processing device is operating in the first primary mode and the trace information from the debug port controller when the processing device is operating in the second mode as determined by the debug port controller.

High-speed debug port using standard platform connectivity

REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.

Robust memory link testing using memory controller

Growing community of inventors

Hillsboro, OR, United States of America

Rony Ghattas