Digital Equipment Corporation

Rony Elia-Shaoul

Joseph Paul Zeh

Bruce A Delagi

In order to incorporate a very high speed memory subsystem into a computer system utilizing unified bus architecture, memory control apparatus associated with the very high speed memory is provided with a first port communicating directly with a system central processor and a second port interfacing with the unified bus. The memory control apparatus may include means for systematically refreshing volatile high speed memories. Multiple processor systems may be realized by taking advantage of the dual port characteristics of the very high speed memory subsystems associated with each central processor.

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Belmont, MA, United States of America

Rony Elia-Shaoul