Intel Corporation

Micron Technology Incorporated

Sae Magnetics (h.k.) Limited

Ronny Ronen

Adi Yoaz

Stephan Jourdan

Boris Ginzburg

Eliezer Weissmann

Lihu Rappoport

Efraim Rotem

Gad Shlomo Sheaffer

Lev Finkelstein

Alon Naveh

Robert Valentine

Alexander D Peleg

Michael Mishaeli

Avi Mendelson

Andrew F Glew

Richard A Uhlig

Doron Rajwan

Nadav Shulman

David A Koufaty

Ehud Cohen

Anil Aggarwal

Antonio Gonzalez

Opher D Kahn

Scott D Hahn

Hong Wang

Edward Thomas Grochowski

Koichi Yamada

Wei Ey Li

Dheeraj R Subbareddy

Eugene Gorbatov

Guy M Therien

John Thomas Shen

Rajesh Bhikhubhai Patel

Ganapati Srinivasa

Konstantin Levit-Gurevich

Robert L Farrell

Michael Bekerman

Doron Orenstien

Mattan Erez

Aviad Cohen

Karthikeyan Karthik Vaithianathan

Stephan J Jourdan

Yoav Zach

Ilya Osadchiy

Baruch Solomon

Bob Valentine

Gregory Pribush

Dmitry Rudoy

Yuval Yosef

Roni Rosner

Guillermo Savransky

Bishara Shomar

Nathaniel Hoffman

Freddy Gabbay

Karthikeyan Vaithianathan

Maury J Bach

George Elias

Doron Orenstein

Xavier Vera

Aamer Jaleel

Paolo L Narvaez

Abraham Mendelson

Jaume Abella

Esfir Natanzon

Oded Lempel

Tong Li

Nicolas I Kacevas

Hisham Abu-Salah

Gadi Haber

Murali M Annavaram

Gershon Kedem

Evgeni Krimer

Jose-Alejandro Pineiro

Ilan Y Spillinger

Yoav Almog

Kenzo Van Craeynest

Stephen J Jourdan

Freddy Gabby

Stephen J Jourday

Avi Mendleson

Yossi Abulafia

Adam De La Zerda

A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

Aggregated page fault signaling and handling

Disclosed embodiments relate to processing logic for performing function operations. In one example, and apparatus includes an execution unit within a processor to execute a code block, power management hardware coupled to the execution unit, wherein the power management hardware is to monitor a first execution of the code block, store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters, read the associated metadata block upon a second execution of the code block, and tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block.

Mechanism for saving and retrieving micro-architecture context

An apparatus is described having multiple cores, each core having: a) a CPU; b) an accelerator; and, c) a controller and a plurality of order buffers coupled between the CPU and the accelerator. Each of the order buffers is dedicated to a different one of the CPU's threads. Each one of the order buffers is to hold one or more requests issued to the accelerator from its corresponding thread. The controller is to control issuance of the order buffers' respective requests to the accelerator.

Mechanism for issuing requests to an accelerator from multiple threads

An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

Apparatus and method for accelerating operations in a processor which uses shared virtual memory

A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. Power management hardware during runtime monitors execution of a code block. The code block has been compiled to have a reserved space appended to one end of the code block. The reserved space includes a metadata block associated with the code block or an identifier of the metadata block. The hardware stores a micro-architectural context of the processor in the metadata block. The micro-architectural context includes performance data resulting from a first execution of the code block. The hardware reads the metadata block upon a second execution of the code block and tunes the second execution based on the performance data.

In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.

Migrating tasks between asymmetric computing elements of a multi-core processor

In one embodiment, a processor includes an accelerator, a decoder to decode a first instruction into a decoded first instruction, and a second instruction into a decoded second instruction, and an execution unit to execute the first decoded instruction to, for a thread executing on the accelerator that is to be placed in an inactive state, cause a save of context information for the thread, and a save of a vector identifying the accelerator corresponding to the context information, and execute the second decoded instruction to read the vector to determine the accelerator to restore saved context information into for the thread, read the saved context information, and restore the saved context information into the accelerator.

Context switching mechanism for a processor having a general purpose core and a tightly coupled accelerator

Aggregated page fault signaling and handline

A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device, such as a graphics processing unit (GPU). The non-CPU may support virtual to physical address mapping and may thus be aware of the memory pages, which may not be pinned but may be accessed by the non-CPU. The non-CPU may notify or send such information to a run-time component such as a device driver associated with the CPU. The device driver may, dynamically, perform pinning of such memory pages, which may be accessed by the non-CPU. The device driver may even unpin the memory pages, which may be no longer accessed by the non-CPU. Such an approach may allow the memory pages, which may be no longer accessed by the non-CPU to be available for allocation to the other CPUs and/or non-CPUs.

Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform

In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

Providing an asymmetric multicore processor system transparently to an operating system

An apparatus is described having multiple cores, each core having: a) an accelerator; and, b) a general purpose CPU coupled to the accelerator. The general purpose CPU has functional unit logic circuitry to execute an instruction that returns an amount of storage space to store context information of the accelerator.

Context switching mechanism for a processing core having a general purpose CPU core and a tightly coupled accelerator

Growing community of inventors

Haifa, Israel

Ronny Ronen