Agilent Technologies, Inc.

Hewlett-Packard Company

Avago Technologies General IP (Singapore) Pte. Ltd.

Ronnie E Owens

Barbara Jean Duffner

Ulrich Knoch

Bert G Pihlstrom

Michael Richter

Charles E Moore

Theodore G Rossin

Larry S Metz

Martin Fischer

Robert B Roze

Thorsten Krueger

A circuit includes a first circuit portion operable as a digital-to-analog converter (DAC) for generating a DAC common mode voltage signal (outp), a second circuit portion having a comparator for comparing the DAC common mode voltage (outp) against a received signal common mode voltage (vsumdc), the comparator providing a single bit output, and a single bit register configured to receive the single bit output of the comparator, the single bit output used to control a feedback circuit, the feedback circuit configured to control the DAC common mode voltage signal.

Digital-to-analog converter (DAC) with common mode tracking and analog-to-digital converter (ADC) functionality to measure DAC common mode voltage

A delay line (DL) circuit used to generate test pattern waveforms has a pulse generating circuit that is used during calibration to generate a pulse signal upon receiving a signal edge. A delay line of the DL circuit receives the pulse signal and delays the pulse signal by a selected time delay. A feedback loop of the DL circuit feeds the delayed pulse signal output from the delay line back to the input of the pulse generating circuit. Receipt of an edge of the fed back pulse signal at the input of the pulse generating circuit causes the pulse generating circuit to generate another pulse signal. The delayed pulse signal output from the delay line can be input to a counter that generates a counter value that is based on the period of oscillation of the delayed pulse signal.

Method and apparatus for calibrating delay lines

Variable delay circuits and methods for delaying a waveform by an adjustable time delay are disclosed herein. One such variable delay circuit comprises a delay range limitation circuit having a first differential input, a first differential output, and a second differential output. The first differential input is configured to receive an input waveform. The first differential output is configured to output the waveform with a maximum delay, and the second differential output is configured to output the waveform with a minimum delay. The variable delay circuit further comprises a delay mixing circuit having second and third differential inputs, first and second control inputs, and a third differential output. The second differential input is connected to the first differential output. The third differential input is connected to the second differential output. The first and second control inputs are configured to receive control voltages Vand V, which are related to a selected time delay. The differential output is configured to output the waveform with the selected time delay.

Variable delay circuit with high resolution

A dual mode amplifier having single ended and differential ended modes of operation using only one set of output pads or terminals. The dual mode amplifier has two differential amplifiers, connected by coupling circuitry, each differential amplifier receiving a pair of differential input signals and having one output terminal. By activating and deactivating the coupling circuitry, the differential amplifiers can operate in two modes using the one set of output terminals. In the singled ended mode, the differential amplifiers operate independently, each converting the differential input signals to a singled ended output signal at their respective output terminals. In the differential mode, the differential amplifiers operate together to provide a pair of differential output signals at the output terminals based upon the pair of input signals.

Selectable single mode or differential mode operation in a single amplifier

Described is a circuit for receiving a differential input signal at two substantially symmetrically built up current paths and for providing an output signal therefrom. At least one current path comprises means for adjusting the timing information of the input signal to the timing information of the output signal. The adjustment can be accomplished by modifying a voltage level in the respective current path until the timing information of the output signals at least substantially represents the timing information of the input signal, e.g. by modifying an impedance or a current in the respective current path. The adjusting of the timing information is executed by applying a defined input signal with a known timing information, comparing the timing information of the resulting output signal with the timing information of the input signal, and modifying at least one voltage level in at least one of the current paths until the timing information of the output and input signals at least substantially match.

Differential circuits with adjustable propagation timing

A method and apparatus are provided for accomplishing virtual deskewing of device-under-test data received by a test system by skewing clock signals instead. In a preferred embodiment, the invention includes a receiver circuit which is capable of operating in a window compare mode to capture a transition of a data signal from either a low data state to a high data state or a high data state to a low data state. The receiver circuit receives a high-level comparator signal and a low-level comparator signal, which when properly deskewed, together indicate what state the data signal is in.

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Fort Collins, CO, United States of America

Ronnie E Owens