Cisco Technology, Inc.

Ronnie B Kon

Kenneth A Moberg

Kristen Marie Robins

Stephen Paul Belair

Daljeet Singh

Arthur B Stine

Systems and methods for replacing software controlling active routers while minimizing impact on network operation are provided by virtue of one embodiment of the present invention. The software replacement process takes advantage of packet processor redundancy. An active packet switching device to be reprogrammed is de-activated and a redundant packet switching device takes over. The no longer active packet switching device is reprogrammed before being reactivated.

Router software upgrade employing redundant processors

A symmetric multiprocessor system includes a first processor and a second processor for executing a multi-threaded process on packets, a first inbound interface and a first outbound interface associated with the first processor, a first task queue accessible for reading by the first processor, a second inbound interface and a second outbound interface associated with the second processor, and a second task queue accessible for reading by at least the first processor. The first inbound interface receives incoming packets and has a first input buffer maintaining a first input queue of the packets for processing by the first processor. The first outbound interface receives packets from the first processor and transmits outgoing packets. The first task queue receives packets output from at least the second processor and maintains another input queue of the packets for processing by the first processor and which are outgoing from the first outbound interface. The second inbound interface receives incoming packets and has a second input buffer maintaining a second input queue of the packets. The second outbound interface receives packets from the second processor and transmits outgoing packets. The second task queue receives packets output from at least the first processor and maintains another input queue of the packets for processing by the second processor and which are outgoing from the second outbound interface. The first processor executes a process thread on packets by requesting the packets from the first input queue and the first task queue in a predetermined manner. The second processor executes a process thread on packets by requesting the packets from the second input queue and the second task queue in a predetermined manner.

Multi-interface symmetric multiprocessor

A high reliability computer system includes a first processing engine (PE), a first memory and a third memory both accessible by the first PE, a second PE, and a second memory and a fourth memory both accessible by the second PE. The first memory contains initialization information for the first PE. The third memory has a location for storing an enable password or a surrogate therefor for the first PE. The second memory contains initialization information for the second PE. The computer system also includes circuitry for switching control of the system from the first PE to the second PE upon detection of a failure of the first PE, and a password passer writing the enable password or a surrogate therefor of the first PE to the fourth memory. Alternatively, a network system includes an authentication, authorization and accounting (AAA) or any other password server having a database for maintaining an enable password for a high reliability computer system. The high reliability computer system includes an interface capable of communicating with the password server over an information bus. The interface obtains the enable password from the password server in response to a request from either one of the first and second PEs.

Password protection for high reliability computer systems

Portions of code containing critical code routines are identified and labeled, then compiled into Dynamic Link Libraries (&ldquo;DLLs&rdquo;) and linked such that the critical code routines are optimally loaded into a reserved address space in the DLL memory space. If supported, cache locking may be enabled for the reserved address space. The portions of source code containing portions of critical code for which execution performance is to be improved are labeled, and the source code is scanned prior to compilation to locate the labeled portions of critical code. A linker is configured to store all the labeled portions of critical code into an Executable and Linking Format (&ldquo;ELF&rdquo;) section header, which is relocated at run-time into a memory space reserved for the portions of critical code. Alternatively, the critical code is compiled and linked into an executable file containing the critical code, and the executable file is optimized by scanning the instruction stream and in-lining the critical code. A prolog and an epilog that accommodates this in-lined critical code is generated, and a single optimized DLL containing the critical code is generated, which is then loaded into a reserved memory space. Robust fault containment is facilitated through the use of code modules implemented as shared libraries that can be loaded and unloaded in a running system by individual processes. These code modules can be replaced individually as defects are found and fixed without requiring replacement of the entire system image or application image. What would normally be a monolithic application is modularized, and the sharing of common code among multiple applications is facilitated.

Performance improvement of critical code execution

Critical code routines are identified, separated from other routines, and compiled into a set of one or more critical dynamic link libraries (&ldquo;DLLs&rdquo;). These are then recognized by a DLL loader and loaded at a reserved address space in the DLL memory space. Once all of the critical DLLs have been loaded, cache locking may be enabled for the reserved address space. Robust fault containment is facilitated through the use of code modules implemented as shared libraries that can be loaded and unloaded in a running system by individual processes. These code modules can be replaced individually as defects are found and fixed without requiring replacement of the entire system image or application image. What would normally be a monolithic application is modularized, and the sharing of common code among multiple applications is facilitated.

Apparatus and method for improving performance of critical code execution

A high reliability computer system includes a first and a second processing engine (PE), circuitry for switching control of the system from the first PE operating as a primary PE to the second PE upon detection of a failure of the first PE, at least one shared resource associated with both the first and second PEs, at least one dedicated resource associated with the first PE and at least one dedicated resource associated with the second PE, a database associated with and accessible by one of the first and second PEs and a configuration engine. The database contains initialization information for the one PE, including a first class of instructions affecting the shared resource and a second class of instructions affecting the dedicated resource of the one PE. The second class of instructions includes setting an enable password or a surrogate therefor for the one PE. The configuration engine is associated with the one PE and is operable in one of a first mode and a second mode. The configuration engine allows the one PE to execute the first and second classes of instructions in the first mode and allows the one PE to execute the second class of instructions in the second mode. The configuration engine may include a classifier for classifying the instructions into the first and second classes. Alternatively, the configuration engine may include the database having a first memory containing the first and second classes of instructions and a second memory containing the second class of instructions.

Method and apparatus for configuration in multi processing engine computer systems

Data storage units, such as flash memory, nonvolatile random access memory and like, are provided with information stored therein, or physically coupled thereto, which indicates, or can be used to determine, remaining or impending end of lifetime of the data storage unit or its components. In a flash memory embodiment, a counter initialized to the number of maximum permissible flash memory erasures is stored in a counter, such as in the header portion of the flash memory. The counter is decremented with each erasure and, as the counter approaches zero, appropriate actions can be taken such as warning the user, support personnel, vendor and the like and/or disabling the flash memory.

Growing community of inventors

San Jose, CA, United States of America

Ronnie B Kon