Spansion LLC.

Roni Kornitz

Mark W Randolph

Darlene G Hamilton

Nicolas Prawitz

Jean-Yves Grall

Bruno Charrat

The claimed subject matter can provide an architecture that interfaces a single slave device such as a UICC smartcard with multiple host controllers. For example, a secondary host can be interfaced between a primary host (e.g., a controller in a cellular phone, a PDA, an MP3 player . . . ) to manage all transactions with the slave device. The secondary host can operate transparently to the primary host and thus does not require any modifications to the primary host. This can be accomplished, e.g., by employing the CMD channel (which is relatively sparsely used by the primary host) to communicate both commands and data with the slave.

Multiple communication channels on MMC or SD CMD line

The claimed subject matter can provide an architecture that interfaces a single slave device such as a UICC smartcard with multiple host controllers. For example, a secondary host can be interfaced between a primary host (e.g. a controller in a cellular phone, a PDA, an MP3 player . . . ) to manage all transactions with the slave device. The secondary host can operate transparently to the primary host and thus does not require any modifications to the primary host. This can be accomplished, e.g. by employing the CMD channel (which is relatively sparsely used by the primary host) to communicate both commands and data with the slave. Moreover, the transactions initiated by the secondary host can be segmented into many smaller fragments and interleaved between transactions initiated by the primary host. In addition, the secondary host can temporarily take on the role of the slave device and affect direct communication with the primary host.

Methods and circuits for performing high speed write (programming) operations in a dual-bit flash memory array. The method includes, for example, erasing a first and second bit of each cell in the array to a first state, programming the first bit of each cell in the array to a second state, and subsequently programming the second bit of one or more cells in the array to one of the first and second state according to the user's data, resulting in fast write (programming) of those second bits. In addition, the circuit includes, for example, a core cell array having dual-bit flash memory cells configured into a plurality of array portions. The circuit further includes a control circuit configured to selectively block erase one of the array portions, wherein in a first phase of the block erase both first and second bit locations of each dual-bit flash memory cell in the one array portion have sufficient charge removed therefrom to achieve a first state. The control circuit is further configured to, in a second phase of the block erase, supply charge to the first bit location of each dual-bit flash memory cell of the one array portion to enable subsequently fast-write of user's data to the second bit location.

Growing community of inventors

Sunnyvale, CA, United States of America

Roni Kornitz