Texas Instruments Corporation

Rongwei Zhang

Abram M Castro

Vikas I Gupta

Yong Lin

Benjamin Stassen Cook

Juan Alejandro Herbsommer

Woochan Kim

Matthew David Romig

Patrick Francis Thompson

James Huckabee

Simon Joshua Jacobs

Steven Alfred Kummerl

Jaimal Mallory Williamson

Jo Bito

Sadia Naseem

Bob Lee

Chien Hao Wang

An integrated filter optical package including an ambient light sensor that incorporates an infrared (IR) filter in an integrated circuit (IC) stacked-die configuration is provided. The integrated filter optical package incorporates an infrared (IR) coated glass layer to filter out or block IR light while allowing visible (ambient) light to pass through to a light sensitive die having a light sensor. The ambient light sensor detects an amount of visible light that passes through the IR coated glass layer and adjusts a brightness or intensity of a display screen on an electronic device accordingly so that the display screen is readable.

Integrated filter optical package

An integrated circuit (IC) package includes a molding having a first surface and a second surface, the first surface opposing the second surface. An interconnect is encased in the molding. The interconnect includes pads situated at a periphery of a side of the IC package. A portion of the pads are exposed at the first surface of the molding. A die pad is situated proximal to the second surface of the molding. The die pad has a first surface and a second surface, the first surface opposing the second surface, and the second surface is circumscribed by the second surface of the molding. A die is mounted on the first surface of the die pad. A heat spreader is mounted on the second surface of the molding and the second surface of the die pad. The heat spreader extends between edges of the second surface of the molding.

IC package with heat spreader

In examples, a semiconductor package comprises a substrate including a conductive layer; a conductive pillar coupled to the conductive layer; and a semiconductor die having first and second opposing surfaces. The first surface is coupled to the conductive pillar. The package also includes a die attach film abutting the second surface of the semiconductor die and a metal layer abutting the die attach film and having a metal layer surface facing away from the die attach film. The metal layer surface is exposed to an exterior of the FCCSP. The package includes a mold compound layer covering the substrate.

Package heat dissipation including a die attach film

A semiconductor device includes a substrate and a semiconductor die including an active surface with bond pads, an opposite inactive surface, and stepped side surfaces extending between the active surface and the inactive surface. The stepped side surfaces include a first planar surface extending from the inactive surface towards the active surface, a second planar surface extending from the active surface towards the inactive surface, and a side surface offset between the first planar surface and the second planar surface. The semiconductor device further includes an adhesive layer covering at least a portion of a surface area of the second surface and attaching the semiconductor die to the substrate.

Semiconductor die with stepped side surface

A leadless integrated circuit (IC) package includes a spaced apart plurality of lead terminals on at least two sides of the leadless IC package, and an IC die including a substrate having at least a semiconductor surface including circuitry coupled to bond pads with the bond pads having bonding features thereon. The bonding features are flip chip bonded to the plurality of lead terminals. Mold compound is above the IC die and between adjacent lead terminals. The lead terminals and the substrate both extend out to have exposed surfaces at edges of the leadless IC package, and the lead terminals also provide a back side bondable contact.

Wafer level derived flip chip package

Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus.

Methods and apparatus for a semiconductor device having bi-material die attach layer

A method includes applying a die attach material to a die pad of an integrated circuit package. The die attach material is employed as a bonding material to the die pad. The method includes mounting an integrated circuit die to the die pad of the integrated circuit via the die attach material. The method includes printing an adhesion deposition material on the die attach material appearing at the interface of the integrated circuit die and the die pad of the integrated circuit package to mitigate delamination between the integrated circuit die and the die pad.

Printed adhesion deposition to mitigate integrated circuit package delamination

A packaged semiconductor device includes a leadframe (LF) having a plurality of laminate-supporting pedestals. A cured first die attach (DA) material is on an outer edge of the pedestals being an ultraviolet (UV)-curing DA material having a photoinitiator or a cured B-stage DA material. A cured thermally-curing DA material is on an area of the pedestals not occupied by the UV-curing DA material. A laminate component having bond pads on a top side is mounted top side up on the plurality of pedestals.

2-step die attach for reduced pedestal size of laminate component packages

Methods and apparatus for semiconductor device having bi-material die attach layer

A method includes applying a die attach material to a die pad of an integrated circuit. The die attach material is employed as a bonding material to the die pad. The method includes mounting an integrated circuit die to the die pad of the integrated circuit via the die attach material. The method includes printing an adhesion deposition material on the die attach material appearing at the interface of the integrated circuit die and the die pad of the integrated circuit to mitigate delamination between the integrated circuit die and the die pad.

Printed adhesion deposition to mitigate integrated circuit delamination

An apparatus for enhancing the thermal performance of semiconductor packages effectively. The concept of this invention is to provide silicon nanowires on the backside of an integrated circuit die to directly attach the die to the substrate, thereby improving the interface between die and substrate, and thus enhancing thermal performance and enhancing reliability by improving adhesion.

Self-adhesive die

The assembly of a chip () attached to a substrate () with wires () spanning from the chip to the substrate is loaded in a heated cavity () of a mold; the wire surfaces are coated with an adsorbed layer of molecules of a heterocyclic compound (); a pressure chamber () of the mold is loaded with a solid pellet () of a packaging material including a polymerizable resin, the chamber being connected to the cavity; the vapor of resin molecules is allowed to spread from the chamber to the assembly inside the cavity during the time interval needed to heat the solid pellet for rendering it semi-liquid and to pressurize it through runners () before filling the mold cavity, whereby the resin molecules arriving in the cavity are cross-linked by the adsorbed heterocyclic compound molecules into an electrically insulating at least one monolayer of polymeric structures on the wire surfaces.

Plastic-packaged semiconductor device having wires with polymerized insulating layer

A packaged IC wherein a portion of the sidewalls of the packaged IC are solderable metal. A method of forming a packaged IC wherein a portion of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal. A method of forming a packaged IC wherein all of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal and a portion of sidewall of the molding compound is solderable metal.

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Dallas, TX, United States of America

Rongwei Zhang