Shanghai Huali Microelectronics Corporation

Rongwei Fan

Yin Long

Qiliang Ni

Hunglin Chen

Kai Wang

Feijue Liu

The present invention provides a method of detecting and measuring the alignment shift of the contacts relative to the gate structures. The method comprises: designing a test model array having different test model regions on the substrate; forming second conductivity type doped well regions, gate structures, and first conductivity type doped active regions in each of the test model regions; forming contacts in each of the test model region; scanning the test model array by an electron-beam inspector to obtain light-dark patterns of the contacts; and detecting and measuring the alignment shift of the contacts relative to the gate structures according to the light-dark patterns of the contacts and the critical dimensions of the transistors in the test model regions.

Method of detecting and measuring contact alignment shift relative to gate structures in a semicondcutor device

A method of inspecting misalignment of a polysilicon gate is disclosed, characterized in forming only NMOS devices in P-wells in a test wafer and utilizing an advanced electron beam inspection tool operating with a positive mode to carry out electrical defect inspection. The method can be applied in precisely figuring out the in-plane misalignment of the polysilicon gates of an in-process semiconductor product and identifying a misalignment tendency therebetween across a wafer by verifying all locations of interest thereon, thus providing a methodology for process window optimization and on-line monitoring and contributing to the manufacturing process and yield improvement.

Method of inspecting misalignment of polysilicon gate

The invention provides a measurement of lateral diffusion of implanted ions in the doped well regions of semiconductor devices comprising: designing a test model having active areas, the P-type and N-type doped well regions of the active areas are separated by STI, and the bottom width of the STI is determined; performing multiple processes on the test model comprising the ion implantation process and the tungsten interconnection process to simulate a semiconductor device structure, wherein during the ion implantation process, in the P-type or N-type doped well regions, only the first procedure of the ion implantation process is performed; scanning the test model, obtaining a light-dark pattern of the tungsten interconnects. The present invention is convenient and accessible and can provide reference to optimize the property of the doped well regions of the semiconductor devices and ensure the yield enhancement.

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Shanghai, China

Rongwei Fan