Qualcomm Incorporated

Philips Healthcare Informatics, Inc.

Rongtian Zhang

Shiqun Gu

Lew G Chua-Eoan

Matthew Michael Nowak

Vidhya Ramachandran

Shashank Sureshchandra Ekbote

Dong Wook Kim

Kenneth Kaskoun

Hung Vuong

Sang Tran

In some aspects, an apparatus includes a processing system that includes one or more processors and one or more memories coupled to the one or more processors. The processing system is configured to send one or more memory access commands to a volatile memory. The one or more memory access commands are associated with a first address. The processing system if further configured to access, based on detecting a row-hammer condition associated with the one or more memory access commands, a physically adjacent row mapping table to determine at least a second address. The first address and the second address correspond to physically adjacent rows within the volatile memory. The processing system if further configured to send one or more row refresh commands to the volatile memory based on the row-hammer condition. The one or more row refresh commands are associated with at least the second address.

Row-hammer condition mitigation using a physically adjacent row mapping table

A capacitor includes a semiconductor substrate. The capacitor also includes a first terminal having a fin disposed on a surface of the semiconductor substrate. The capacitor further includes a dielectric layer disposed onto the fin. The capacitor still further includes a second terminal having a FinFET compatible high-K metal gate disposed proximate and adjacent to the fin.

FinFET capacitor circuit

Some implementations provide a package that includes a first die and a second die adjacent to the first die. The second die is capable of heating the first die. The package also includes a leakage sensor configured to measure a leakage current of the first die. The package also includes a thermal management unit coupled to the leakage sensor. The thermal management unit configured to control a temperature of the first die based on the leakage current of the first die.

Thermal management of tightly integrated semiconductor device, system and/or package

Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.

Small form factor magnetic shield for magnetorestrictive random access memory (MRAM)

An integrated circuit (IC) module with a lead frame micro-needle for a medical device, and methods of forming the IC module are described. The methods include forming a lead frame blank including a micro-needle integrally formed therein. The micro-needle may be bent beyond an initial lower side of the lead frame blank. The initial lower side may be joined with a protection layer such that the bent micro-needle is embedded in the protection layer, which may be removably attached to the initial lower side and the bent micro-needle. An IC component may be affixed to an upper side of the lead frame blank. The IC component and an upper surface of a core of the lead frame blank may be encapsulated with a molding compound forming a packaging of the IC module. Removal of the protection layer may expose the bent micro-needle projecting away from the packaging.

Integrated circuit module with lead frame micro-needles

FinFET compatible capacitor circuit

A method for fabricating a native device is presented. The method includes forming a gate structure over a substrate starting at an outer edge of an inner marker region, where the gate structure extends in a longitudinal direction, and performing MDD implants, where each implant is performed using a different orientation with respect to the gate structure, performing pocket implants, where each implant is performed using a different orientation with respect to the gate structure, and concentrations of the pocket implants vary based upon the orientations. A transistor fabricated as a native device, is presented, which includes an inner marker region, an active outer region which surrounds the inner marker region, a gate structure coupled to the inner marker region, and first and second source/drain implants located within the active outer region and interposed between the first source/drain implant and the second source/drain implant.

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San Diego, CA, United States of America

Rongtian Zhang