Hrl Laboratories, LLC

Transphorm Inc.

Rongming Chu

Yu Cao

Karim S Boutros

David F Brown

Adam J Williams

Umesh Kumar Mishra

Zijian “Ray” Li

Andrea Corrion

Robert Coffie

Yifeng Wu

Miroslav Micovic

Keisuke Shinohara

Mary Y Chen

Danny M Kim

Shawn D Burnham

Thaddeus D Ladd

Xu Chen

Primit A Parikh

Rakesh K Lal

Likun Shen

Ilan Ben-Yaacov

Brian G Hughes

Zijian Ray Li

Alexandros Margomenos

Dean C Regan

Joel C Wong

Daniel Yap

Sameh G Khalil

Daniel M Zehnder

Andrew S Pan

Andrey A Kiselev

Samuel Kim

Zijan Ray Li

Andrew Pan

Zijian "Ray" Li

Brian Hughes

A field effect transistor having at least a gate, source, and drain electrodes and a semiconductor channel for controlling transport of charge carriers between the source and drain electrodes, the gate being insulated from the channel by an dielectric, at least a portion of the dielectric disposed between the gate electrode and the semiconductor channel being doped or imbued with the an element which if doped or imbued into a semiconductor material would cause the semiconductor to be p-type. The p-type element used to dope or imbue the gate dielectric is preferably Mg.

Doped gate dielectrics materials

Methods of in situ fabrication and formation of horizontal nanowires for a semiconductor device employ non-catalytic selective area epitaxial growth to selectively grow a semiconductor material in a selective area opening of predefined asymmetrical geometry. The selective area opening is defined in a dielectric layer to expose a semiconductor layer underlying the dielectric layer. The non-catalytic selective area epitaxial growth is performed at a growth temperature sufficient to also in situ form a linear stress crack of nanoscale width that is nucleated from a location in a vicinity of the selective area opening and that propagates in a uniform direction along a crystal plane of the semiconductor layer in both the semiconductor layer and the dielectric layer as a linear nanogap template. The semiconductor material is further selectively grown to fill the linear nanogap template to in situ form the nanowire that is uniformly linear.

In situ fabrication of horizontal nanowires and device using same

A field effect transistor (FET) includes a III-nitride channel layer, a III-nitride barrier layer on the channel layer, a first dielectric on the barrier layer, a first gate trench extending through the first dielectric, and partially or entirely through the barrier layer, a second dielectric on a bottom and walls of the first gate trench, a source electrode on a first side of the first gate trench, a drain electrode on a second side of the first gate trench opposite the first side, a first gate electrode on the second dielectric and filling the first gate trench, a third dielectric between the first gate trench and the drain electrode, a second gate trench extending through the third dielectric and laterally located between the first gate trench and the drain electrode, and a second gate electrode filling the second gate trench.

III-nitride field-effect transistor with dual gates

A III-nitride power handling device and the process of making the III-nitride power handling device are disclosed that use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity. An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of AlN and GaN. Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations. The disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.

Digital alloy based back barrier for P-channel nitride transistors

Semiconductor device having in situ formed horizontal nanowire structure

A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material.

FET transistor on a III-V material structure with substrate transfer

A laser or light emitter for operation at a cryogenic temperature includes a single quantum well layer, an n-type barrier layer directly on a first surface of the single quantum well layer, and a p-type barrier layer directly on a second surface of the single quantum well layer opposite the first surface of the single quantum well layer. The single quantum well layer is between the p-type barrier layer and the n-type barrier layer and the compositions of the n-type barrier layer and the p-type barrier layer are graded.

Low modulation-voltage cryogenic diode structure

Doped gate dielectric materials

A half bridge circuit includes a sapphire substrate, a GaN upper switch on the sapphire substrate, a GaN lower switch on the sapphire substrate and coupled to the GaN upper switch, a first conductor coupled to the upper switch, a second conductor coupled to the lower switch, and a capacitor. A portion of the first conductor and a portion of the second conductor are on a plane vertically separated from the upper switch and the lower switch by a height, and the capacitor is coupled between the portion of the first conductor and the portion of the second conductor.

GaN-on-sapphire monolithically integrated power converter

A device for storing and/or transferring quantum data. The device has a plurality of elongate semiconductor structures arranged in side by said with each elongate semiconductor structure having a quantum well layer of one semiconductor material disposed between upper and lower layers of a different semiconductor material which share the same or essentially the same crystalline structure as that of the quantum well layer. Neighboring ones of the elongate semiconductor structures share a region forming a constriction between the neighboring ones of the elongate semiconductor structures. Also disclosed is a a method of adjusting exchange coupling between laterally coupled quantum wells in a quantum device having sidewalls, the method including: defining the sidewalls by etching a crystalline structure along lattice planes of said crystalline structure, the crystalline structure, after the sidewalls are etched, having a corrugated shaped with protuberances and grooves on opposing major surfaces thereof, and controlling a ratio of the distances (i) between opposing grooves on the opposing major surfaces of the crystalline structure and (ii) between opposing protuberances on the opposing major surfaces of the crystalline structure.

Etched spin-qubit for high temperature operation

Lateral PN junctions and diodes and transistors comprising lateral PN junctions and methods used in making such devices are disclosed. A method of fabricating a lateral PN junction, can comprise: conformally growing p&#x2212;GaN material on a n&#x2212;GaN vertical surface extending vertically from an n&#x2212;GaN horizontal surface on an n&#x2212;GaN drift layer to form a first PN junction, wherein the n&#x2212;GaN horizontal surface extends horizontally from the n&#x2212;GaN vertical surface and the n&#x2212;GaN horizontal surface has a layer of dielectric material formed on the n&#x2212;GaN horizontal surface that extends from the p&#x2212;GaN surface.

Lateral GaN PN junction diode enabled by sidewall regrowth

Growing community of inventors

Agoura Hills, CA, United States of America

Rongming Chu