Freescale Semiconductor,inc.

Nxp Usa, Inc.

Motorola Corporation

Maxim Integrated Products, Inc.

Nxp B.v.

North Star Innovations Inc.

Motorola Freescale Semiconductor

Ronghua Zhu

Vishnu Khemka

Amitava Bose

Todd C Roggenbauer

Vijay Parthasarathy

Tahir Arif Khan

Xin Lin

Bernhard Grote

Jiang-kai Zuo

Hongning Yang

Zhihong Zhang

Paul Hui

Xu Cheng

Weixiao Huang

Saumitra Raj Mehrotra

Yujing Wu

James Gordon Boyd

Xiaoqiu Huang

Todd Roggenbauer

Michael C Butner

John M Pigott

Randall C Gray

Patrice Besse

Rouying Zhan

Ljubo Radic

Pierre Turpin

Maarten Jacobus Swanenberg

Stephen J Cosentino

Jeffrey J Braun

Jean-Philippe Laine

Adolfo C Reyes

Jan Claes

Matthew Bacchi

Keith Jackoski

Laurent Segarra

Pete Rodriquez

Eric Ooms

Shifeng Shen

Russell Schaller

Vijay Parthasarthy

Jianhua He

Yue Fu

Van Wong

Tahir A Khan

Vishnu K Khemka

In one embodiment, a semiconductor die includes a polycrystalline semiconductor resistor structure (poly resistor structure). The poly resistor structure includes a resistive path between a first terminal and a second terminal. The poly resistor structure includes a first region having a net first conductivity type dopant concentration located in the resistance path and a second region having a net second conductivity type dopant concentration located in the resistance path. A silicide structure is located on both a first portion of the first region and a first portion of the second region to electrically connect the first portion of the first region and the first portion of the second region. In some embodiments, poly resistor structures with different conductivity type regions can be connected together.

Polycrystalline semiconductor resistor

A capacitor includes an electrode implemented in an electrode well of a substrate. The electrode well has a net N-type dopant concentration. The capacitor includes an electrode implemented in a conductive structure located above the substrate. The electrodes are separated by a dielectric layer located between the electrodes. A first tub region having a net P-type conductivity dopant concentration is located below and laterally surrounds the electrode well and a second tub region having a net N-type conductivity dopant concentration is located below and laterally surrounds the first tub region and the electrode well.

Capacitor with an electrode well

A method for manufacturing a semiconductor device includes forming a plate structure over an isolation region. A drain electrode electrically connected to a drift region underlying the isolation region is formed, wherein the drain electrode is separated from a first location of the plate structure by a first distance along a central axis of an active area of the semiconductor device in a direction of a current flow between a source and a drain of the semiconductor device, the drain electrode is separated from a second location of the plate structure by a second distance along a line parallel to the central axis and within the active area. The first distance is less than the second distance.

LDMOS with an improved breakdown performance

A testing method and apparatus is disclosed for testing an integrated circuit device () which has a dedicated ground bias pad () connected across a high voltage electrostatic discharge clamp circuit () to a well-driving ground pad () by applying a first voltage to the dedicated ground bias pad to bias a wafer substrate () while simultaneously applying a second voltage to the well-driving ground pad to bias the well region (), where the first and second voltage create a stressing voltage across a buried insulator layer () in the integrated circuit device so that a screening test can be conducted to screen for a defect () in the buried insulator layer by measuring a leakage current.

Screening method and apparatus for detecting deep trench isolation and SOI defects

A device () includes a substrate (-) with an upper semiconductor layer, buried semiconductor layer, and a DTI structure (-) defining an active device region; a dummy LDMOS device () in the active device region which includes a grounded drain (D) in a drift region (), a source (S, S) in a body region () which extends to contact the buried semiconductor layer, a gate electrode (G-G) formed so that the source and at least part of the gate electrode are connected with the body implant region, and a buffering semiconductor layer portion () adjacent the DTI structure; and one or more active LDMOS devices () positioned in the active device region to be separated from the DTI structure by the dummy LDMOS device () which reduces an electric field across the sidewall insulator layer () in the DTI structure.

Apparatus for extension of operation voltage

An apparatus includes a first trench formed in a semiconductor layer. The first trench has a first width and a first depth. A second trench is formed in the semiconductor layer. The second trench has a second width and a second depth. The first width is wider than the second width. A buried dielectric layer is disposed between a bottom semiconductor surface of the semiconductor layer and a substrate. The buried dielectric layer contacts a first bottom surface of the first trench. A liner dielectric is formed on the first bottom surface and a first sidewall of the first trench. A first layer is formed on the liner dielectric. A second layer is formed on the first layer and extends to the substrate through an opening formed on the first bottom surface.

Deep trench isolation and substrate connection on SOI

A method for improving breakdown voltage of a Laterally Diffused Metal Oxide Semiconductor (LDMOS) includes biasing a first well of a Field Effect Transistor (FET) to a first voltage. The first well is laterally separated from a second well. An isolation ring is charged to a second voltage in response to the first voltage exceeding a breakdown voltage of a diode connected between the isolation ring and the first well. The isolation ring laterally surrounds the FET and contacts a buried layer (BL) extending below the first well and the second well. A substrate is biased to a third voltage being less than or equal to the first voltage. The substrate laterally extends below the BL and contacts the BL.

LDMOS with diode coupled isolation ring

An apparatus comprises a Laterally Diffused Metal Oxide Semiconductor (LDMOS) comprising a drain connectable to a drift region and a source connectable to a body region. A diode comprises a cathode electrically coupled to the drift region, wherein during an operating condition, the anode is charged to a bias voltage less than a high voltage applied to the drain and greater than a low voltage applied to the source. The anode is laterally displaced from the drain by a first distance. A first deep trench isolation (DTI) is proximate to the source and disposed to laterally surround the LDMOS. A shield junction is proximate to the first DTI and on an opposite side of the source, and electrically connected to the anode.

Deep trench and junction hybrid isolation

A method for reducing transistor sensitivity to shallow trench isolation defects (STI) includes filling a trench formed in a substrate of a semiconductor device, at least partially, with a first oxide, the trench defines an STI and includes a defect extending from the substrate. A mask defines a planar area within the isolation region including a first lateral distance between an edge of the mask and an edge of the isolation region. The first oxide is at least partially removed beneath the planar area with an oxide etch to expose a top portion of the defect. The top portion of the defect is removed with a semiconductor etch. After removing the top portion of the defect, the trench is at least partially filled with a second oxide. A field plate of a split-gate transistor is formed over the STI.

Method for making high voltage transistors insensitive to needle defects in shallow trench isolation

A semiconductor device includes a drain region for a transistor, a drain active area directly below the drain region, a drift area directly below an insolation structure, and an accumulation area directly below a gate structure of the transistor. The semiconductor device includes a first selectively doped implant region of a first concentration of a first conductivity type extending to a first depth. The first selectively doped implant region is located in the drift area, the drain active area, and the accumulation area. The semiconductor device includes a second selectively doped implant region of a second concentration of the first conductivity type and extending to a second depth less than the first depth. The second concentration is less than the first concentration. The second selectively doped implant region is located the drain active area, but not in the accumulation area. The second selectively doped implant region occupies a lateral portion of the drain active area that the first doped region does not occupy.

Semiconductor device with drain active area

An example laterally diffused metal oxide semiconducting (LDMOS) device includes a semiconductor substrate of a first conductivity type, active MOS regions, and a lightly-doped isolation layer (LDIL) of a second conductivity type. The active MOS regions include source and drain regions and a plurality of PN junctions. The LDIL is formed above and laterally along the semiconductor substrate, and located between the semiconductor substrate and at least a part of the active MOS regions. The LDIL is doped with dopant of the second conductivity type to cause, in response to selected voltages applied to the LDMOS device, the plurality of PN junctions to deplete each other and to support a voltage drop between the source and drain regions along the LDIL.

Laterally diffused metal oxide semiconducting devices with lightly-doped isolation layers

The present disclosure teaches a Field-Effect Transistor (FET) configured as a diode to provide ESD protection. The field-effect transistor has its gate, source, and body connected to a common power supply rail. A low-density doped drain region extends in a length direction beyond the gate sidewall spacers of the transistor to provide a lower leakage current than would otherwise be exhibited by the protection device.

Electro-static discharge protection device and method of making

Embodiments of a device are provided, including a semiconductor substrate including an active device area; a body region disposed in the semiconductor substrate within the active device area, wherein a channel is formed within the body region during operation; a doped isolation layer disposed in the semiconductor substrate underneath the active device area, the doped isolation layer including an opening positioned under the active device area; and a lightly-doped isolation layer disposed in the semiconductor substrate underneath the active device area, the lightly-doped isolation layer positioned at least within the opening and in electrical contact with the doped isolation layer, wherein the doped isolation layer and the lightly-doped isolation layer form a doped isolation barrier that extends across an entire lateral extent of the active device area.

Partially biased isolation in semiconductor device

A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate, a body region disposed in the semiconductor substrate within the doped isolation barrier and in which a channel is formed during operation, an isolation contact disposed at the semiconductor substrate and to which a voltage is applied during operation, and a plurality of reduced surface field (RESURF) layers disposed in the semiconductor substrate, the plurality of reduced surface field (RESURF) layers being arranged in a stack between the body region and the isolation contact.

Semiconductor device isolation with RESURF layer arrangement

A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate within the doped isolation barrier, having the first conductivity type, and in which a channel is formed during operation, and a plurality of reduced surface field (RESURF) layers disposed in the semiconductor substrate. The plurality of RESURF layers are arranged in a stack between the body region and the doped isolation barrier. The plurality of RESURF layers include an upper layer having a second conductivity type, a lower layer having the second conductivity type, and an isolation coupling layer disposed between the upper and lower layers, in contact with the doped isolation barrier, and having the first conductivity type.

Semiconductor device isolation via depleted coupling layer

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Chandler, AZ, United States of America

Ronghua Zhu