Gigadevice Semiconductor (beijing) Inc.

Gigadevice Semiconductor (shanghai) Inc.

Gigadevice Semiconductor (xian) Inc.

Ronghua Pan

Jiang Yi Liu

Jianjun Zhang

Sai Zhang

Hong Hu

Qingming Shu

Daping Liu

An X16 nonvolatile memory has 16 input/output (I/O) ports, identified as I/O ports [15:0], and adopts a conversion method, which allows the memory to operate in an X16 mode or in an X8 mode. The method includes receiving a first user command that is sent by an upper computer and belongs to a user mode; determining a disabling command for a module path of the high-bit I/O ports [15:8] according to the first user command; and executing the disabling command and disabling the module path for controlling the high-bit I/O ports [15:8] of the memory so as to operate in an X8 mode.

Mode conversion method and apparatus for a nonvolatile memory

An enhanced Flash chip of SPI interface and a method for packaging chip, to solve the problems of high design complexity, long design period and high design cost. The chip comprises SPI FLASH and RPMC which are packaged integrally; the SPI FLASH and the RPMC comprise an independent controller, respectively; the same IO pins in SPI FLASH and RPMC are mutually connected and are connected to the same external sharing pin of the chip. The SPI FLASH and the RPMC further comprise an internal IO pin, respectively, in which the internal IO pin of SPI FLASH is connected with the internal IO pin of RPMC, and the internal mutual communication between the SPI FLASH and the RPMC is achieved through the mutually connected internal IO pins. Thus, it is possible to reduce the package size, decrease the cost of design, shorten design period and improve chip performance.

SPI interface enhanced flash chip and chip packaging method

An enhanced Flash chip and a method for packaging chip are provided to solve the problems of high design complexity. The enhanced Flash chip comprises: a FLASH and a RPMC packaged integrally, wherein the same IO pins in the FLASH and in the RPMC are mutually connected and are connected to the same external sharing pin of the chip; an external instruction is transmitted to the FLASH and the RPMC through the external sharing pin of the chip, and the controller of the FLASH and the controller of the RPMC respectively judge whether to execute the external instruction; and the FLASH and the RPMC further comprise internal IO pins, respectively, the internal IO pins of the FLASH and the internal IO pins of the RPMC are mutually connected, and internal mutual communication between the FLASH and the RPMC is performed through the pair of mutually connected internal IO pins.

Enhanced flash chip and method for packaging chip

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Beijing, China

Ronghua Pan