Emc IP Holding Company LLC

Dell Products Inc.

Emc Corporation

Rong Yu

Peng Wu

Peng Yin

Michael J Scharland

Lixin Pang

Stephen Richard Ives

Jeremy O'Hare

Orit Levin-Michael

Ramesh Doddaiah

Adi Ofer

Malak Alshawabkeh

Yechiel Yochai

Jiahui Wang

John W Lefferts

Bin Dai

Mark J Halstead

Dan Aharoni

Qun Fan

Ran Margalit

Shao Hu

Jeffrey R Nelson

Benjamin W Yoder

Gilad Sade

Mohammed Asher

Ningdong Li

Pei-Ching Hwang

Cynthia Burns

Barak Bejerano

Daniel E Rabinovich

Jingtong Liu

Venkata Khambam

Brian Asselin

Arieh Don

David Meiri

Alexandr Veprinsky

Haim Kopylovitz

Amnon Naamad

Deepak Vokaliga

Michael Ferrari

Sandeep Chandrashekhara

Ning Wu

Ajith Balakrishnan

Zvi Gabriel Benhanokh

Anoop Raghunathan

Benjamin Randolph

Earl Medeiros

Magnus E Bjornsson

Kaustubh S Sahasrabudhe

Jack Fu

Sunil Gumaste

Bradley Allen Bowlin

Roderick Klinger

Abhilash Sanap

Ian Adams

Ravish Sachdeva

Pankaj Soni

Mohammed Asher Vt

Robert Lucey

Benjamin A F Randolph

James McGillis

Stephen F Modica

John Madden, Jr

Tao Gong

William N Eagle

Bing Liu

Emulation modules running on a single-board compute node have allocations of cores of a multi-core processor. The emulation modules are configured to donate underutilized cores or available CPU cycle units to a shared pool that can be used by other emulation modules running on the board. Emulation modules that require additional processing resources borrow cores or CPU cycle units from the shared pool. The emulation modules dynamically donate and retract cores or CPU cycle units from the shared pool based on utilization of allocated cores.

Dynamic CPU core sharing

One or more aspects of the present disclosure relate to distributing write destaging amongst a storage array's boards. In embodiments, an input/output (IO) workload is received at a storage array. In addition, a write IO request in the IO workload is directed to a target board of a plurality of boards of the storage array based on one or more performance-related hyperparameters of each board. Further, write data of the write IO request to a storage device is destaged by the target board.

Distributed write destaging

As front-end write IO operations occur, the front-end write IO operations are allocated slots of global memory and mapped to slices of back-end tracks. A back-end write destage manager allocates back-end slices to aging buckets based on the number of write operations pending destage for the given back-end slice. As global memory destage pressure increases, the back-end write destage manager uses a weighted bucket table to increase the weight back-end slices with larger numbers of front-end tracks that are occupying the larger slots of global memory. This results in back-end slices that are owed data from front-end tracks occupying larger front-end slot sizes to be placed in aging buckets with shorter aging times. These back-end slices are thus more quickly selected to be destaged, thus causing a larger percentage global memory slots of the largest slot size to be made available to be allocated to subsequent host IO write operations.

Global memory slot size based destage prioritization

A Ransomware Activity Detection System (RADS) characterizes historic read/write IO activity on a storage volume, and also characterizes historic data characteristics of the storage volume, such as the percentage reducibility of the data held in the storage volume. The RADS monitors the storage volume to identify differences between current read/write IO activity and historic read/write IO activity, as well as difference between current data characteristics of the storage volume and historic data characteristics of the storage volume. When the RADS detects a significant difference in read/write IO activity on a storage volume, that is coupled with a significant changes to the data characteristics of the storage volume, the RADS protects the storage volume and generates an alert of the possible occurrence of a ransomware attack. Protection may occur prior in connection with any bulk read operation to proactively protect storage volumes against ransomware attacks.

Method and apparatus for detecting the occurrence of a ransomware attack on a storage volume

One or more aspects of the present disclosure relate to performant destaging of write pending (WP) data to disk. In embodiments, an input/output (IO) workload is received at a storage array. Additionally, the IO workload can include an IO request with a random write request. Further, a write destage context for write-pending (WP) data corresponding to the random write request can be generated by a data services engine of the storage array. In addition, using the write destage context, a disk adapter (DA), at a backend of the storage array, is enabled to destage write-pending (WP) data without reading from a target write location of the random write request on a storage device on the storage array.

Performant write pending data destaging

In a storage system where Front-End (FE) tracks do not correspond to Back-End (BE) tracks on a one-to-one basis, a Logical Entry (LE) table is implemented in the BE processes to enable masking to occur on BE Logical Entry values rather than on BE tracks. An LE watch table is used to correlate LE values with BE tracks. When a RAID slice destage is initiated to move data from the FE tracks to BE tracks implementing the RAID slice, the LE watch table is used to identify a respective set of LE values that correspond to each respective RAID slice BE track. Entries of the BE mask corresponding to the LE values identified from the LE watch table are used to identify FE tracks that contain data to be included in the RAID slice destage. Metadata is retrieved for each identified FE track, and the RAID slice destage is implemented.

Logical back-end device entry-based slice write destage

A storage system is configured to accept subsequent versions of write data on a given track to multiple respective slots of shared global memory. A track index table presents metadata at the track level, and can hold up to N slots of data. All slots of shared global memory holding data owed to the source volume and to snapshots of the source volume are bound to the track in the track index table. Each time a write occurs on a track, the track index table is used to determine when a write pending slot for the track is owed to a snapshot copy of the storage volume. When a write pending slot contains data that is owed to a snapshot copy of the source volume, a new slot is allocated to the write IO and bound to the track in the track index table.

Multiple version write pending support in shared global memory

Embodiments of the present disclosure relate to managing communications between slices on a storage device engine. Shared slice memory of a storage device engine is provisioned for use by each slice of the storage device engine. The shared slice memory is a portion of total storage device engine memory. Each slice's access to the shared memory portion is controlled.

Slice memory control

Data deduplication techniques may use a fingerprint hash table and a backend location hash table in connection with performing operations including fingerprint insertion, fingerprint deletion and fingerprint lookup. Processing I/O operations may include: receiving a write operation that writes data to a target logical address; determining a fingerprint for the data; querying the fingerprint hash table using the fingerprint to determine a matching entry of the fingerprint hash table for the fingerprint; and responsive to determining that the fingerprint hash table does not have the matching entry that matches the fingerprint, performing processing including: inserting a first entry in the fingerprint hash table, wherein the first entry includes the fingerprint for the data and identifies a storage location at which the data is stored; and inserting a second entry in a backend location hash table, wherein the second entry references the first entry.

Techniques for efficient data deduplication

Aspects of the present disclosure relate to data cache management. In embodiments, a logical block address (LBA) bucket is established with at least one logical LBA group. Additionally, at least one LBA group is associated with two or more distinctly sized cache slots based on an input/output (IO) workload received by the storage array. Further, the association includes binding the two or more distinctly sized cache slots with at least one LBA group and mapping the bound distinctly sized cache slots in a searchable data structure. Furthermore, the searchable data structure identifies relationships between slot pointers and key metadata.

Cache memory architecture and management

A Random Read Miss (RRM) distribution process monitors execution parameters of first, second, and third emulations of a storage engine, and distributes newly received read operations between the emulations. The RRM distribution process assigns newly received read operations to the first emulation, unless the CPU thread usage of the first emulation or the response time of the first emulation meet a first set of criteria. The RRM distribution process secondarily assigns newly received read operations to the second emulation, unless the CPU thread usage of the second emulation or the response time of the second emulation meet a second set of criteria. The RRM distribution process assigns all other newly received newly received read operations, that are not assigned to the first emulation or to the second emulation, to the third emulation. Distribution of read IOs between the emulations enables the storage engine to increase IOPs while minimizing response time.

Method and apparatus for distributing read operations between emulations in a storage engine

Aspects of the present disclosure relate to data cache management. In embodiments, a storage array's memory is provisioned with cache memory, wherein the cache memory includes one or more sets of distinctly sized cache slots. Additionally, a logical storage volume (LSV) is established with at least one logical block address (LBA) group. Further, at least one of the LSV's LBA groups is associated with two or more distinctly sized cache slots based on an input/output (IO) workload received by the storage array.

Embodiments of the present disclosure relate to throttling processing threads of a storage device. One or more input/output (I/O) workloads of a storage device can be monitored. One or more resources consumed by each thread of each storage device component to process each operation included in a workload can be analyzed. Based on the analysis, consumption of each resource consumed by each thread can be controlled.

Throttling processing threads

Aspects of the present disclosure relate to asynchronous memory management. In embodiments, an input/output (IO) workload is received at a storage array. Further, one or more read-miss events corresponding to the IO workload are identified. Additionally, at least one of the storage array's cache slots is bound to a track identifier (TID) corresponding to the read-miss events based on one or more of the read-miss events' two-dimensional metrics.

Memory management based on read-miss events

A synchronous destage process is used to move data from shared global memory to back-end storage resources. The synchronous destage process is implemented using a client-server model between a data service layer (client) and back-end disk array of a storage system (server). The data service layer initiates a synchronous destage operation by requesting that the back-end disk array move data from one or more slots of global memory to back-end storage resources. The back-end disk array services the request and notifies the data service layer of the status of the destage operation, e.g. a destage success or destage failure. If the destage operation is a success, the data service layer updates metadata to identify the location of the data on back-end storage resources. If the destage operation is not successful, the data service layer re-initiates the destage process by issuing a subsequent destage request to the back-end disk array.

Synchronous destage of write data from shared global memory to back-end storage resources

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West Roxbury, MA, United States of America

Rong Yu