Stmicroelectronics Gmbh

Sgs-thomson Microelectronics Limited

Rong Yin

David C McClure

Mehdi Zamanian

Tom Youssef

Thomas A Coker

Glenn T O'Rourke

David Charles Mcclure

A reset ramp control structure and method is described. A fast ramp down condition of a monitored voltage is detected and used to force the state of system reset. Delay between fast ramp detection and the forcing of system reset is adjustable. Operation is adaptable to include all DC power systems. The reset ramp control structure provides operational protection during fast ramp down conditions when standard reset circuitry may not be operational.

Reset ramp control

A circuit and method are disclosed for monitoring the state of at least one switch. The circuit may include a first circuit, coupled to a switch, for detecting whether the switch is in one of a closed state and an open state and generating a signal having a value based upon the detection. The circuit may further include a second circuit, coupled to the first circuit, for configuring the first circuit to selectively detect the switch switching from a normally open state and to selectively detect the switch switching from a normally closed state.

Configurable circuit and method for detecting the state of a switch

A method and circuit are disclosed for detecting the performance of an oscillator circuit. In particular, the circuit may detect a signal, such as the output of the oscillator circuit, failing to oscillate as desired. The second circuit may be capable of detecting whether the signal oscillates at a frequency that is less than a predetermined frequency. The second circuit may include timing circuits for determining whether the signal remains in a first logic state for at least a predetermined period of time and whether the signal remains in a second logic state for at least the predetermined period of time.

Detection circuit and method for an oscillator

A circuit and method are disclosed for detecting activation of a switch, such as a mechanical switch. The circuit may include a first circuit for temporarily driving the second terminal of the switch to a second logic level. A second circuit, coupled to the switch, senses a voltage level of the second terminal of the switch and generates an output signal representative of the voltage sensed. A sequential logic circuit is responsive to the output signal of the second circuit so as to maintain a logic value representative of the switch having been closed.

Circuit and method for detecting the state of a switch

A method and circuit are disclosed for enabling an oscillator circuit to oscillate a predetermined period of time following completion of a power-up operation. The circuit may include a counter having a control for receiving a control signal from a system power-on-reset circuit, and a clock input. A ring oscillator has an output coupled to the clock input of the counter.

Startup circuit and method for starting an oscillator after power-off

A circuit and method are disclosed for controlling current dissipated by an oscillator circuit. The circuit includes a current source adapted to source current to or sink current from the oscillator circuit. A control circuit is adapted to count a predetermined period of time following the occurrence of an event, such as completion of a power-up operation. An output of the control circuit, having a value indicative of whether the predetermined period of time has elapsed, is coupled to a control input of the current source. In this way, the output of the control circuit sets a current level sourced to or sunk from the oscillator circuit by the current source.

Control circuit and method for a crystal oscillator using a timer

A circuit and method are disclosed for monitoring the voltage level of an unregulated power supply. The circuit includes a voltage reference circuit for generating a first reference voltage signal and a trim circuit which generates a trimmed reference voltage signal based upon the first reference voltage signal. A comparator compares the unregulated power supply voltage to the trimmed reference voltage signal and asserts an output signal based upon the comparison. The output signal is fed back as an input to the trim circuit so that the trim circuit provides a hysteresis effect.

Power supply detection circuitry and method

A temperature compensated clock and method of clocking systems are provided. The clock preferably has an oscillator for generating an oscillating waveform signal at a preselected frequency and a frequency divider responsive to the oscillator for dividing the frequency of the oscillating waveform signal. A temperature monitoring circuit is positioned responsive to a voltage input signal independent of temperature and a voltage input signal proportional to temperature for monitoring temperature variations. A temperature compensating circuit, preferably including a programmable scaling circuit, is responsive to the frequency divider and the temperature monitoring circuit for scaling the divided frequency of the generated waveform and thereby advantageously produces a temperature compensated output timing signal.

Low power, cost effective, temperature compensated real time clock and method of clocking systems

A method and circuit are disclosed for measuring temperature. An exemplary embodiment of the present invention includes a first oscillator circuit that generates a first signal having a frequency that is dependent upon a sensed temperature. Difference circuitry determines a difference in frequency between the first signal and the second signal having a frequency that is substantially independent of temperature, and generates a difference signal having a number of pulses thereon based upon the difference. A counter circuit is responsive to the difference circuitry for offsetting a predetermined temperature level based upon the pulses appearing on the difference signal, to obtain an output signal indicative of the sensed temperature.

Temperature sensing circuit and method

A frequency test circuit ( ) includes a built-in self test (BIST) circuit ( ) which provides for testing of a frequency generating circuit such as an oscillator circuit ( ). The test circuit ( ) includes circuit stages ( ) which help produce a reference signal ( ) which has substantially the same frequency as that produced by the oscillator circuit ( ) when it is operational. Since the low current oscillator circuit ( ) can fail at any one of the divider or level shifting stages ( ), the test circuit ( ) can determine if the reference signal and the output signal of the oscillator have substantially the same frequency and produce a test condition signal indicative of either a pass or failed test at test port ( ).

Built-in frequency test circuit for testing the frequency of the output of a frequency generating circuit

A reference voltage trim circuit includes a voltage follower receiving the reference voltage to be trimmed, with one or more resistive loads providing predefined voltage shifts serially connected between the output of the voltage follower and the output of the trim circuit. The voltage follower includes a current mirror differential amplifier receiving the reference voltage at one input and the output of the voltage follower at the other input, and a transistor with a resistive load connected between the power supply voltages and receiving the output of the current mirror differential amplifier at the transistor's gate. The resistive loads provide varying preselected voltage drop and are each shunted by corresponding fuses, with the entire series of resistive loads shunted by a master fuse. To trim the reference voltage, at least the master fuse is blown, together with the fuse(s) shunting resistive loads which combine to result in the desired trim voltage. Pass gates control which end of the resistive load series is connected to the output of the voltage follower and which is connected to the output of the trim circuit. To decrement the reference voltage, a first end is connected to the output of the voltage follower and the second end is connected to trim circuit output; to increment the reference voltage, the second end of the resistive load series is connected to the voltage follower output and the first end is connected to the trim circuit output.

Reference voltage adjustment

The present invention is a temperature sensor which is based on the actual temperature coefficients of a device in the circuit, rather than a predetermined threshold voltage that varies across different devices. This temperature sensor includes a circuit which determines the temperature of a device. More particularly, CMOS circuit is provided which uses a current source to generate charge and discharge voltages applied to a capacitor. These voltages are dependent on the temperature coefficient of a resistor in the current source. The charge and discharge times are then used to determine a frequency which is dependent on the temperature coefficient of the resistor. Thus, the temperature is sensed based on the output frequency of the circuit. Additionally, the present invention includes a mechanism which allows the temperature sensor to be activated or deactivated as needed.

Low voltage/low power temperature sensor

Low power, cost effective, temperature compensated, real time clock and

A frequency test circuit (200) includes a built-in self test (BIST) circuit (212) which provides for testing of a frequency generating circuit such as an oscillator circuit (100). The test circuit (200) includes circuit stages (202-208) which help produce a reference signal (210) which has substantially the same frequency as that produced by the oscillator circuit (100) when it is operational. Since the low current oscillator circuit (100) can fail at any one of the divider or level shifting stages (106-112), the test circuit (200) can determine if the reference signal and the output signal of the oscillator have substantially the same frequency and produce a test condition signal indicative of either a pass or failed test at test port (214).

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Coppell, TX, United States of America

Rong Yin