Broadcom Corporation

Shanghai United Imaging Microelectronics Technology Co., Ltd.

Rong Wu

Tianwei Li

Jieyou Zhao

Chun-Ying Chen

Young J Shin

Jiangfeng Wu

Yin Tang

Chia-Jen Hsu

Tao Wang

Wei-Te Chou

Wei-Ta Shih

Karthik Raviprakash

Wenliang Ren

Mingfeng Chen

Longheng Luo

Haichao Zhang

Disclosed are an analog-to-digital conversion circuit, an analog-to-digital conversion device, and a digital x-ray imaging system. The analog-to-digital conversion circuit includes a first reference voltage source, a second reference voltage source, a first analog-to-digital converter connected to the first reference voltage source, a second analog-to-digital converter connected to the second reference voltage source, a connecting circuit connected to the first analog-to-digital converter and the second analog-to-digital converter, respectively, and a current source having negative temperature coefficient configured to be connected to the first reference voltage source and the second reference voltage source, respectively.

Analog-to-digital conversion circuit, analog-to-digital conversion device, and digital x-ray imaging system

Disclosed are a readout circuit, a signal quantizing method, a signal quantizing device, and a computer device. The readout circuit includes: a signal sampler, including a plurality of channels; a plurality of integrators, connected to the plurality of channels and having a one-to-one relationship with the plurality of channels; a signal processor, including a first operational amplifier, a sampling input of the first operational amplifier being connected to outputs of the plurality of integrators, respectively; and an analog-digital converter. An input of the analog-digital converter is connected to an output of the first operational amplifier.

Readout circuit, signal quantizing method and device, and computer device

Disclosed are a readout circuit, an offset voltage eliminating method and device, a computer device, and a non-transitory computer-readable storage medium. The readout circuit includes an object quantizer and an offset voltage elimination circuit. The offset voltage elimination circuit includes a correction circuit and a calibration circuit, an input of the correction circuit is connected to an output of the object quantizer, a compensation input of the calibration circuit is connected to an output of the current compensator, and a reference input of the calibration circuit is connected to the output of the object quantizer.

Readout circuit, offset voltage eliminating method, computer device, and storage medium

An analog-to-digital converter (ADC) is used for dynamic tracking nonlinearity correction. The correction employs an analog sampling technique to determine the signal derivative by measuring the derivative current arising from sampling an analog input signal undergoing analog-to-digital conversion, at the sampling instant. The analog derivative sampling technique achieves significant reduction in power consumption with less complexity compared with a digital approach, with strong improvements in HD, SDFR, and IMmeasures.

Dynamic tracking nonlinearity correction

An analog-to-digital converter (ADC) utilizing a capacitor array during multiple conversion stages and amplifier sharing across multiple lanes. In various embodiments, the ADC includes N lanes, each of the lanes including a capacitor array. A plurality of switches coupled to each capacitor array selectively redistributes a sampled charge during N clock phases corresponding to N conversion stages, the conversion stages including a sampling stage performed on an analog input signal, at least one quantization stage, and N&#x2212;2 multiplying digital-to-analog conversion (MDAC) stages for generating residue voltages. The MDAC stages utilize a plurality of N&#x2212;2 amplifiers shared by the N lanes. In operation, each amplifier may be used in an interleaved manner to support, during a given clock phase, an MDAC stage of one of the lanes of the ADC. Likewise, one or more comparators of a lane may be leveraged to perform multiple quantization stages during the N clock phases.

Interleaved multiple-stage capacitor and amplifier sharing in an ADC

A system includes a pipeline analog-to-digital converter as a first stage to process an input signal, and a successive approximation register (SAR) analog-to-digital converter as a second stage to process the input signal. The SAR analog-to-digital converter includes a power adjustment element to adjust a reference voltage of the SAR analog-to-digital converter to match a full scale voltage of the pipeline-analog-to-digital converter.

System and method for integration of hybrid pipeline

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Irvine, CA, United States of America

Rong Wu