Lsi Logic Corporation

Seeq Technology, Incorporated

Rong-Hui Hu

Stephen F Dreyer

Stephen F Dryer

A multiple-register-access-capable device includes a serial port coupled to a plurality of registers. The multiple-register-access-capable device is controlled by a state machine. Information in one of the registers identifies whether the device is in a single-register or multiple-register mode. The state machine which controls the device operates in a single-register mode if the bit is disabled and operates in a multiple-register mode if the bit is enabled. In single-register mode, the device operates in a manner known in the prior art whereby a single register is identified for reading or writing and data is then either written into the register or read out from the register in response to a write or read request. In multiple register mode, data is written into or read out from all registers in a selected group of registers in the device in response to the write or read request. When the device of the present invention is in multiple-register access mode, a read or write operation addressed to a selected register is interpreted as a request to read or write from all registers in a defined group of registers and the state machine directs the operation of the device to accomplish a read from or write to all of the registers in the group. When the device is in single-register mode, operations addressed to the selected register cause normal read or write operation to be executed with respect to that register.

State machine for selectively performing an operation on a single or a plurality of registers depending upon the register address specified in a packet

State machine for selectively performing an operation on a single or a

The invention provides a method and system in which a single pin coupled to an integrated circuit (IC) chip is used to enter configuration information at a power-up time or a reset time (collectively referred to herein as a 'reset time' or 'reset interval'), and is also used to display output information during normal operation. The pin is coupled to a memory device, so as to store configuration information received during the reset interval. The pin is also coupled to an output driver controlled by a gate which combines output data with a signal indicating reset time, so as to put the output driver into a high impedance state during reset time when the input configuration data is being stored into the device and to drive the pin with the output value during non-reset times. Thus, a user of the IC may cause the memory to receive configuration information from the pin at power-up or during another reset time, while having the pin output normal data at times other than the reset interval.

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Union City, CA, United States of America

Rong-Hui Hu