Mosel Vitelic Corporation

United Microelectronics Corp.

Rong-ching Chen

Mao-Song Tseng

Chin-lin Lin

Jy-Hwang Lin

Ching-Chun Huang

Su-Wen Chang

Su-wen Chang

First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as &#x2212;6V&#x2dc;12V, &#x2212;12V&#x2dc;6V, &#x2212;9V&#x2dc;9V etc.

Method for forming single-level electrically erasable and programmable read only memory operated in environment with high/low-voltage

In the invention, a photoresist layer is first spread on a semiconductor structure, and then using a photomask with a specially designed pattern exposes the photoresist layer. Next, the photoresist layer is developed to form a patterned photoresist layer. Thereafter, using the patterned photoresist layer as a mask, a trench is formed in the semiconductor structure by selective etching. The pattern of the photomask according to the invention is formed as in the following steps. At first, a first pattern extending in a first direction and having a first side and a second side that is opposite to the first side is formed. Next, a second pattern extending in a second direction that is perpendicular to the first direction is formed in such a way that an end of the second pattern is connected with the first side of the first pattern. Thereafter, a concave edge is formed on the second side to substantially face the second pattern. The distance between the first side and the second side is shortened due to the presence of the concave edge. As a result, the depth of the dimples developed at the intersection points of the dimple lines is greatly reduced when a polysilicon layer is deposited on the trench formed according to the invention.

Method for improving the dimple phenomena of a polysilicon film deposited on a trench

A method for forming a self-aligned contact for a trench DMOS transistor comprises: providing a semiconductor substrate; etching a trench into the semiconductor substrate at a selected location on the surface of the semiconductor substrate; forming a first dielectric layer that covers the semiconductor substrate and walls of the trench; forming a plug in the trench, which comprises a step of depositing a semiconductor layer that covers the semiconductor substrate and fills in the trench, and a step of etching the semiconductor layer until the plug is below the trench for about 0.2 to 0.3 micron; forming a second dielectric layer on the plug; and forming a conductive layer over the second dielectric layer and the surface of the semiconductor substrate for ohmic contact regions.

Self-aligned contact for trench DMOS transistors

Growing community of inventors

Taichung, Taiwan

Rong-ching Chen