Cadence Design Systems, Inc.

Rong Chen

Dan Nicolaescu

Nupur B Andrews

Poojan Rajeshbhai Shah

He Xiao

James Sangkyu Kim

Nenad Nedeljkovic

Nenad Nedeljkovi

Jiayuan Chen

An approach of the present disclosure includes an algorithm to encode an instruction set of a domain-specific processor automatically in an optimal way, and which yields area-effective hardware. Instruction operands and opcodes can be encoded separately or at the same time. Instructions are not encoded one by one but can be encoded in groups, and instructions are grouped automatically. The decoding logic of control signals for each group of instructions, such as register read enable and write enable, is fed to a logic minimizer to obtain an encoding constraint matrix, and the encoding of each instruction in each instruction group is done using an optimal state assignment method.

Method and apparatus for encoding of processor instruction set

An approach includes the use of a description of instructions for invoking hardware accelerator and for a hardware accelerator to execute those instructions. In some embodiments, the instructions for invoking hardware accelerator and for a hardware accelerator to execute those instructions are described using a single language. These descriptions are then compiled into other languages for use in tool chains for generating simulators (a hardware and instruction set simulator and a hardware accelerator simulator). In some embodiments, the approach illustrated herein can be combined with state machine functionality to manage the execution of instructions that require multiple states. In some embodiments, the approach illustrated herein can be combined with an external register file for transferring information between a processor and a hardware accelerator.

Method, product, and system for integrating a hardware accelerator with an extensible processor

In some examples, a polar decoder for implementing polar decoding of a codeword can be configured to implement alogarithmic likelihood ratio (LLR), an even bit, and an odd bit buffer, respectively. The polar decoder can be configured to employ a list-to-buffer mapping state register for the LLR buffer for loading LLR values for each path at a given stage of a decoding graph. The polar decoder can be configured to update and store LLR values for each path at the given stage. The polar decoder can be configured to employ a list-to-buffer mapping state register for the even bit buffer for loading even bit values from the even bit buffer and loading odd bit values from the odd bit buffer, and updating even or odd bit values for each path at the given stage of the decoding graph.

Polar decoder processor

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San Jose, CA, United States of America

Rong Chen