Motorola Corporation

Ronen Paz

Vladimir Koifman

Michael Zarubinsky

In a radio circuit (299) that forwards a signal pair (I,Q) by first ( , I) and second ( , Q) channels, by converting the signal pair (I,Q) from a digital form (I , Q ) to an analog form (I , Q ), a gain controller ( ) monitors differences between the overall gains (G , G ) in the channels and corrects a gain imbalance by feeding back a gain determining control signal (W) to one of the channels. The gain controller ( ) has digital comparators ( ) at the inputs ( ) of the channels and analog comparators at the outputs ( ) of the channels. Intrinsic offsets of the analog comparators are determined and compensated by subtracting corresponding offsets from the digital comparators.

Gain controller with comparator offset compensation for circuit having in-phase and quadrature channels

In a radio circuit ( ) that forwards a signal pair (I,Q) by a first channel ( , I) and by a second channel ( , Q), a gain controller ( ) monitors differences between the overall gains (G , G ) in the channels and corrects a gain imbalance by feeding back a gain determining control signal (W) to one of the channels. The controller has first ( ) and second ( ) pluralities of single-bit comparators, operating at a high sampling rate, to monitor the signal pair at the channel inputs ( ) and at the channel outputs ( ), respectively, and to provide difference signals (&Dgr;X,&Dgr;Y) to an integrator ( ) that calculates the gain control signal (W) at a decimated sampling rate (F ).

Gain controller for circuit having in-phase and quadrature channels, and method

A device and a method for canceling DC offset resulting from digital to analog conversion, wherein the device is coupled to a digital to analog comparator (i.e.&mdash;DAC), the device comprising of: an adder, coupled to the DAC, for adding a digital input signal IN(n) to a compensation signal CS(w&minus;1), and sending the sum of IN(n) CS(w&minus;1) to the DAC. An analog comparator, coupled to the DAC, for sampling the output signal OUT(t) of the DAC, for comparing the sampled signal ACS(n) to a first reference voltage VREF and for outputting a signal ACO(n) which represents the result of the comparison between ACS(n) and VREF. A DAC emulator, coupled to the DAC, for compensating for a time lapse between the appearance of a digital input signal IN(n) appearing at the input of the adder and an OUT(t), wherein OUT(t) resulted from IN(n). A digital comparator for receiving the output signals DES(n) of the DAC emulator, comparing DES(n) to a second reference value DREF and outputting a signal DCO(n) which represents the result of the comparison between DES(n) to DREF, and an offset calculation unit, coupled to the analog comparator and to the digital comparator for comparing ACO(n) and DCO(n) and sending to the adder, a compensation signal CS(n) which represents the result of the comparison between ACO(n) and DCO(n). The analog and digital comparator are driven by a clock signal which is not correlated to IN(n).

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Hadera, Israel

Ronen Paz