Unifabrix Ltd.

Intel Corporation

Ronen Aharon Hyatt

Ethan Sharon Hyatt

Gaya Opal Hyatt

Ben-Zion Friedman

Vadim Sukhomlinov

Eliel Louzoun

Linden Cornett

Anjali Singhai Jain

Andrey Chilikin

Mark Debbage

Robert J Munoz

Noam Elati

Sarig Livne

Nadav Turbovich

Nir Tiser

Danny Volkind

Embodiments of a switch enabling multiple hosts to concurrently access and share resources of a Single Logical Device (SLD). The switch includes first and second upstream switch ports (USPs) coupled to first and second hosts, and a downstream switch port (DSP) coupled to the SLD. The first USP communicates with the first host according to a first Compute Express Link (CXL) protocol, the second USP communicates with the second host according to a second CXL protocol, and the DSP communicates with a first CXL SLD component according to a third CXL protocol. A Resource Provisioning Unit (RPU) terminates the first, second, and third CXL protocols, and exposes second and third virtualized SLDs, which utilize resources of the first SLD component, to the first and second hosts, respectively. Optionally, the first, second, and third CXL protocols are CXL.mem protocols.

Scalable virtualization of GPUs and compute accelerators in a switch providing CXL resource-as-a-service of memory, NVMe or RDMA networking via SLD agnostic provisioning

Embodiments for communicating using a switch having multiple sets of switch ports, which can generate abstractions for compute nodes and accelerators in a switched Compute Express Link (CXL) interconnect, enabling any-to-any connectivity between hosts and devices. A first set of switch ports couples hosts and/or devices with a first virtual to physical binding. A second set couples a Resource Provisioning Unit (RPU) with the first virtual to physical binding. The first binding binds at least some of the first and/or second sets of switch ports to a first set of Virtual CXL Switches (VCSs). A third set couples the RPU to a second virtual to physical binding. A fourth set couples additional hosts and/or devices with the second virtual to physical binding. And the second virtual to physical binding binds at least some of the third and/or fourth sets of switch ports to a second set of VCSs.

Abstraction of compute nodes and accelerators in a switched CXL interconnect

This invention pertains to a system optimized for reutilizing allocated underutilized or unused allocated DRAM, comprising a first host, a second host, and a resource composer, interconnected via CXL. Both hosts run packaged computing environments (PCEs), which may be containers or virtual machines, and are equipped to handle respective processes, P1 and P2. The resource composer is tasked with receiving data related to P1's memory usage from a kernel module on the first host, identifying underutilized DRAM mapped to P1, and subsequently remapping it to P2's address space on the second host. This process involves the use of CXL.mem commands, which are then translated into appropriate CXL.cache or CXL.io commands for DRAM access based on the mapping.

Memory mapping and CXL translation to exploit unused remote memory in a multi-host system

Embodiments for communicating using a switch configured to establish multiple types of communication routes. First and second upstream switch ports (USPs) communicate with first and second hosts according to first and second Compute Express Link (CXL) protocols, respectively. A downstream switch port (DSP) communicates with a device according to a third CXL protocol. The switch couples the first USP to the DSP via a first route traversing a single Virtual CXL Switch (VCS), and couples the first USP to the second USP via a second route traversing two VCSs. Optionally, the switch includes a Resource Provisioning Unit (RPU) coupling the two VCSs of the second route, terminating the first and second CXL protocols, and translating between CXL messages conforming to the first and second CXL protocols.

Switched protocol transformer for high-performance computing (HPC) and AI workloads

Embodiments for communicating using a switch. A first Virtual CXL Switch (VCS) routes messages, conforming to a first CXL protocol, from a first switch port to a Resource Provisioning Unit (RPU). A second VCS routes messages, conforming to a second CXL protocol, from the RPU to the second switch port. The RPU terminates the first and second CXL protocols and translates at least some of the messages conforming to the first CXL protocol to at least some of the messages conforming to the second CXL protocol. Optionally, the first CXL protocol comprises CXL.mem, the second CXL protocol comprises CXL.cache, and the RPU manages snoop and invalidation message flows and maintains transaction order requirements.

Elastic multi-directional resource augmentation in a switched CXL fabric

Embodiments for communicating between a Compute Express Link (CXL) host and a CXL device. A CXL Endpoint receives, from the host, first messages conforming to a first CXL.io protocol and second messages conforming to a first non-CXL.io protocol. A CXL Root Port receives, from the device, third messages conforming to a second CXL.io protocol and fourth messages conforming to a second non-CXL.io protocol. A computer terminates the first CXL.io protocol, processes at least some of the first messages without translating and sending corresponding translated first messages to the device, terminates the first non-CXL.io protocol, translates at least a quarter of the second messages, and makes the translated second messages available to the CXL Root Port for communication with the device. Optionally, each of the first and second non-CXL.io protocols is selected from at least one of CXL.mem or CXL.cache.

Host-to-device CXL communication including multi-fabric bridging, also over NVLink, UALink, and ethernet

Embodiments for communicating between Compute Express Link (CXL) hosts. A first CXL Endpoint receives, from a first host, first messages conforming to a first CXL.io protocol and second messages conforming to a first non-CXL.io protocol. A second CXL Endpoint receives, from a second host, third messages conforming to a second CXL.io protocol and fourth messages conforming to a second non-CXL.io protocol. A computer terminates the first CXL.io protocol, processes at least some of the first messages without translating and sending corresponding translated first messages to the second host, terminates the first non-CXL.io protocol, translates at least a quarter of the second messages, and makes the translated second messages available to the second CXL Endpoint for communication with the second host. Optionally, each of the first and second non-CXL.io protocols is selected from at least one of CXL.mem or CXL.cache.

Host-to-host communication with selective CXL non-transparent bridging

Dynamic provisioning of resources in a datacenter improves the utilization efficiency of compute, memory, storage, and network resources, while maintaining flexibility to meet changing demands. Embodiments herein disclose protocol-aware provisioning of resources over Compute Express Link (CXL) fabrics, enabling multi-protocol pooling and disaggregation of resources, including memory and workload-specific accelerators such as GPUs and DSAs. In some embodiments, a Resource Provisioning Unit (RPU) facilitates intent-based protocol translations and mappings between address spaces, potentially enabling the creation of large-scale compute-memory fabrics that may utilize both coherent and non-coherent Non-Transparent Bridging (NTB) between multiple protocols in a single system, serving as the underlying infrastructure for executing workloads such as Large-Language Models (LLMs) and Deep Learning Recommendation Models (DLRMs). Some embodiments also optimize low-latency communication between processes running on different nodes by enabling host-to-host memory provisioning for libraries such as OpenMP, Pthreads, or CUDA, which can utilize shared memory.

Protocol-aware provisioning of resource over CXL fabrics

Embodiments for communicating using a switch including Virtual CXL Switches (VCSs), upstream switch ports (USPs), and downstream switch ports (DSPs), enabling flexible mapping between switch ports and entities. Each VCS includes an upstream virtual PCIe-to-PCIe bridge (vPPB) coupled to one or more downstream vPPBs. A first virtual to physical binding is configured to bind USPs to upstream vPPBs, and a second virtual to physical binding is configured to bind DSPs to downstream vPPBs. Optionally, the switch further includes a Resource Provisioning Unit (RPU) to terminate CXL protocols and translate at least some CXL messages, and the first and second bindings bind the RPU to respective upstream and downstream vPPBs.

Reconfigurable multi-layer virtual binding in a CXL switch fabric

Embodiments for communicating between first and second hosts according to CXL.mem and CXL.cache protocols. A computer translates a CXL.mem M2S RwD with a Tag, received by a CXL Type 2 or Type 3 device (EP1) from the first host, to a CXL.cache D2H Req with a CQID. A CXL Type 1 or Type 2 device (EP2) sends the D2H Req to the second host, and receives a CXL.cache H2D Rsp with the CQID and a UQID. EP1 sends a CXL.mem S2M NDR with the Tag to the first host, and EP2 sends a CXL.cache D2H Data message with the UQID to the second host. Optionally, EP1 receives and terminates CXL.io/PCIe Configuration Request TLPs from the first host, the M2S RwD further includes a first physical address and Data, and the D2H Req further includes a second physical address.

Translating between CXL.mem and CXL.cache write transactions

Memory has been playing a major role in the performance, scalability and applicability of General Compute systems, and more recently, in realizing Generative Artificial Intelligence (GenAI) and High-Performance Computing (HPC) systems that scale to thousands of GPUs, CPUs and special-purpose Accelerators. Embodiments herein disclose efficient software-defined protocol terminations and protocol translations utilizing Compute Express Link (CXL), including translations between CXL.mem and CXL.cache protocols. Also disclosed are CXL-based systems, Resource Provisioning Units (RPUs), and Memory Fabric Switches enabling dynamic memory pooling and sharing, host-to-host communication utilizing CXL.mem, CXL.cache and CXL.io, intent-based protocol translations, and optionally seamless interactions between CXL, UALink, NVLink, and/or Ethernet protocols, utilizing a broad range of semantics including IO, Cache, and Memory, optimizing memory access and reducing latency. Some embodiments also enable scalability, flexibility and security in high-performance architectures suited for data centers and next-generation computing environments.

Translating between CXL.mem and CXL.cache read transactions

Examples described herein relate to a device indicating a number of available interrupt messages that is more than physical resources available to store the available interrupt messages and allocating one or more physical resources to provide one or more interrupt messages based on allocation of the one or more interrupt messages to a destination entity. The destination entity can request a maximum permitted allocation of interrupt messages regardless of interrupt message use level. The destination entity can request a maximum permitted allocation of interrupt messages regardless of interrupt message use level and allocate the requested maximum permitted allocation of interrupt messages for use in a configuration region of a device. However, based on unavailability of a physical resource to store a first interrupt message, allocation of the first interrupt message to a destination entity may not be permitted.

Dynamic interrupt provisioning

Technologies for filtering network traffic on ingress include a network interface controller (NIC) configured to parse a header of a network packet received by the NIC to extract data from a plurality of header fields of the header. The NIC is additionally configured to determine an input set based on the field vector, retrieve a matching list from a plurality of matching lists, and compare the input set to each of the plurality of rules to identify a matching rule of the plurality of rules that matches a corresponding portion of the input set. The NIC is further configured to perform an action on the network packet based on an actionable instruction associated with the one of the plurality of rules that matches the corresponding portion of the input set. Other embodiments are described herein.

Technologies for filtering network traffic on ingress

Technologies for processing network packets a compute device with a network interface controller (NIC) that includes a host interface, a packet processor, and a network interface. The host interface is configured to receive a transaction from the compute engine, wherein the transaction includes latency-sensitive data, determine a context of the latency-sensitive data, and verify the latency-sensitive data against one or more server policies as a function of the determined context. The packet processor is configured to identify a trust associated with the latency-sensitive data, determine whether to verify the latency-sensitive data against one or more network policies as a function of the identified trust, apply the one or more network policies, and encapsulate the latency-sensitive data into a network packet. The network interface is configured to transmit the network packet via an associated Ethernet port of the NIC. Other embodiments are described herein.

Technologies for managing a latency-efficient pipeline through a network interface controller

Techniques to schedule transmission of a packet from a computing platform include calculating adjustments to portions of the packet to cause corrections to at least one portion of the packet. An adjustment to a scheduled transmission of the packet is made based on the corrections.

Growing community of inventors

Haifa, Israel

Ronen Aharon Hyatt