International Business Machines Corporation

Ronald Xavier Arroyo

William Elton Burky

Roger Donell Weekly

Gary Franklin Goth

Bret Peter Elison

Thoi Nguyen

Terrance Wayne Kueper

Joaquin Hinojosa

Kenneth A Bird

James T Hanna

William A Ciarfella

Tricia A Gruwell

Guy L Guthrie

Jody B Joyner

Michael Norman Day

Bradly George Frey

John Stephen Muhich

Gary Dean Anderson

Steven T Pancoast

Gary T Hunt

Jimmie Darius Edrington

Khuong Huu Pham

Lawrence Joseph Merkel

Charles Gordon Wright

Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an operating junction temperature. In some embodiments, the measured junction temperature may be the operating junction temperature anticipated for the DUT in a customer installation. In other embodiments, the tester may comprise logic to calculate a projected, operating junction temperature based upon the measured junction temperature and known differences between the tester and a customer installation. Upon determining the operating junction temperature for the DUT at the customer installation, the operating junction temperature is compared against a maximum junction temperature for proper operation of the DUT. Advantageously, the maximum junction temperature may be varied based upon the project objective for a line of DUTs.

Systems and arrangements to assess thermal performance

A shared memory multiprocessor (SMP) data processing system includes a store buffer implemented in a memory controller for temporarily storing recently accessed memory data within the data processing system. The memory controller includes control logic for maintaining coherency between the memory controller's store buffer and memory. The memory controller's store buffer is configured into one or more arrays sufficiently mapped to handle I/O and CPU bandwidth requirements. The combination of the store buffer and the control logic operates as a front end within the memory controller in that all memory requests are first processed by the control logic/store buffer combination for reducing memory latency and increasing effective memory bandwidth by eliminating certain memory read and write operations.

Method and apparatus for managing memory operations in a data processing system using a store buffer

A method and apparatus for improving direct memory access and cache performance utilizing a special Input/Output or &ldquo;I/O&rdquo; page, defined as having a large size (e.g., 4 Kilobytes or 4 Kb), but with distinctive cache line characteristics. For Direct Memory Access (DMA) reads, the first cache line in the I/O page may be accessed, by a Peripheral Component Interconnect (PCI) Host Bridge, as a cacheable read and all other lines are non-cacheable access (DMA Read with no intent to cache). For DMA writes, the PCI Host Bridge accesses all cache lines as cacheable. The PCI Host Bridge maintains a cache snoop granularity of the I/O page size for data, which means that if the Host Bridge detects a store (invalidate) type system bus operation on any cache line within an I/O page, cached data within that page is invalidated, the Level and Level ((L /L ) caches continue to treat all cache lines in this page as cacheable). By defining the first line as cacheable, only one cache line need be invalidated on the system bus by the L /L cache in order to cause invalidation of the whole page of data in the PCI Host Bridge. All stores to the other cache lines in the I/O Page can occur directly in the L /L cache without system bus operations, since these lines have been left in the 'modified' state in the L /L cache.

Method and apparatus with page buffer and I/O page kill definition for improved DMA and L1/L2 cache performance

A method and apparatus of allowing processors of different speeds to be used in a multi-processor system are disclosed. The method and apparatus comprise a programmable array logic (PAL) or field programmable gate array (FPGA) that detects each of the processors maximum speed and selects a speed common to all of the processors as the operating speed of the processors. The method and apparatus also adjust the system clock to match the speed of the processors.

Multi-processor system using processors of different speeds

A mechanism is provided in a microprocessor bus interface to eliminate the turnabout in those cases where the same slave is involved in consecutive read data bus tenures or where the same master and slave are involved in consecutive write data bus tenures. A new optional signal is added to the bus interface, called pre-last transfer acknowledge. The signal is asserted by the slave one cycle before the last transfer acknowledge signal is asserted. The signal is intended to be received by the system's bus arbiter. If the current data tenure and the next data tenure are both read operations directed to the same slave (such as the memory controller) or both write operations from the same master to the same slave, then the arbiter may grant the data bus to the master of the next data tenure the cycle following the assertion of the pre-last transfer acknowledge indicator. This allows the arbiter to grant the bus a cycle earlier than it normally could (where it would have to see the final transfer acknowledge signal before it could grant the bus). Thus, the bus turnaround cycle is eliminated and data bus bandwidth is increased by up to twenty percent.

Addition of pre-last transfer acknowledge signal to bus interface to

A system and method for checking the test logic contained in a computer memory system during POST such that any errors can be determined and made available to the system software prior to beginning processing operations. Single and double bit errors are induced which the ECC logic must identify and correct. The CPU compares the data that is written to memory with the data that is read back. Thus, since it is known that an error occurred, due to the induced error provided by the present invention, identical data will verify that the ECC correction logic is working properly. More specifically, a multiplexer is provided in the data write path which substitutes a constant set of identical bits for the actual data generated by the CPU. ECC bits are generated based on the actual generated test data, rather than the inserted identical bits. The substituted data bits and generated ECC bits are then stored in memory. An error condition is identified when the data and ECC code is read back from memory. The correction logic then corrects the data, in the case of a single bit error, such that the data read by the CPU is the same as the originally generated data.

Method for testing ECC logic

Data bus steering logic routes data between various byte lanes of the system bus. Additionally, control signals are provided which allow the connected device and the steering logic to communicate and respond to requests made by the CPU. The steering logic provides a path between the attached device and the byte lanes of the system bus, to which the device is not directly connected. During load and store operations data is transferred via the steering logic and directly between the device and CPU on to the portion of the system bus that it is directly connected to. The steering logic includes a multiplexer, latch, buffer, driver and the like for each lane of data on the system bus. For example, if the system bus is 64 bits wide and a 32 bit device is connected to one-half of the bus, the steering logic will provide a path from the 32 bit device to the other 32 bits of the system bus not directly connected to the device. Thus, during a 64 bit load operation, 32 bits are provided through the steering logic and driven on to the bus. The other 32 bits of data are then retrieved and driven on to the system bus by the 32 bit device. In this example, there are two paths provided by the steering logic since a 32 bit device has half the data width of a 64 bit bus. If 8 bit devices were to be connected to a 64 bit bus, then there would be 8 data paths since the 64 bit bus has eight times the data width of an 8 bit device.

Steering logic to directly connect devices having different data word

A clocking circuit connected to a processor for regulating processor operation and including a control circuit that produces a clock signal at a first frequency or for producing a clock signal at a designated one of a plurality of other selectable frequencies in response to a change signal from the processor. The control circuit is connected to a designating circuit that provides a signal to the control circuit to designate one of the selectable frequencies. In the preferred embodiment, the clocking circuit includes a register addressable by the processor and a frequency generator that generates several signals having unique frequencies. The processor may designate one of the frequencies as the clocking frequency by providing the appropriate data to the register. Upon the occurrence of an external event such as a DMA request or an interrupt, the control circuit will provide the clocking signal at a predetermined frequency.

Multi-frequency clock generation with low state coincidence upon latching

A method and apparatus for powering down a computer system while saving the state of the system at power down is disclosed. The system maintains the capability to suspend the execution of an application program operating on the system at any point and resuming execution of the application program at that same point at a later time. The time at which the system may be powered down and then powered back up again is totally arbitrary and depends only upon the user of the system. At the time the system is powered off, the contents of all active registers as well as the states of all I/O devices in the system are stored in a special save area of system memory. This special save area is provided with power during the suspended time in order to retain the state of the system at the time it was powered down. By using this special save suspend area, the main memory area of the system is available to any application programs independently of the system save memory requirements. Additionally, the system may be powered on and off under software control thereby providing the capability for unattended system operation using an alarm function.

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Austin, TX, United States of America

Ronald Xavier Arroyo