Intel Corporation

Other

Ronald W Swartz

Yick Yaw Ho

Andrew M Volk

Mikal Hunsaker

Su Wei Lim

Vui Yong Liew

Akira Kakizawa

Syed S Islam

Yoon San Ho

David Stewart Dunning

Huimin Chen

Andrew W Martwick

Ken Drottar

Luke A Johnson

Lily Pao Looi

Michael W Leddige

Zale Theodore Schoenborn

Bruce A Tennant

Poh Thiam Teoh

Rohit R Verma

Bryan L Spry

Robert R Fulton

Dennis J Miller

Hooi Kar Loo

John Maddux

Tea M Lee

Young Min Park

Jennifer Chin

Keith A Jones

Yueming Jiang

Ram Livne

Hui Shi

Paul A Jolly

John L Baudrexl

Tony M Tarango

L Mark Elzinga

Rajashri Doddamani

Vladislav Tsirkin

Donald Rush

Meetul Goyal

David R Mulvihill

Theodor Mulder

Jagannadha Rao V V V Rapeta

Athourina Gevergiz

A sharpening device. In one aspect, the sharpening device includes: a sharpening assembly including a sharpening unit and a rod coupled to the sharpening assembly; a retainer assembly; a coupler for coupling the sharpening assembly to the retainer assembly; an attachment device coupled to the retainer assembly for coupling the retainer assembly to a head of a blade to be sharpened.

Sharpening device

Method and apparatus associated with clocking synchronization are disclosed herein. In various embodiment, a method for communication comprises: entering a clock training period, on successful performance of clock training handshake; entering a start static phase measurement (SSPM) sequence of clock training period, receiving a recovered clock; and processing the recovered clock to determine parts-per-million (PPM) differences, to be subsequently applied to compensate for the PPM differences determined during subsequent clocking synchronization. Linking training is performed after the subsequent clocking synchronization. In various embodiments, clocking synchronization comprises SSC synchronization. Other embodiments are also described and claimed.

Clocking synchronization method and apparatus

Described is an apparatus which comprises: a first capacitor coupled to a first input pad; a second capacitor coupled to second input pad; a first resistor coupled to the second capacitor; a third capacitor coupled in series with the first resistor; a second resistor coupled in series with the third capacitor and also coupled to the first capacitor; and a differential amplifier coupled to the first and second capacitors and to the first and second resistors.

Method and apparatus for passive continuous-time linear equalization with continuous-time baseline wander correction

A first state of an interconnect protocol is entered. A particular signal is sent according to the protocol to a device over a link. During the first state, it is detected that a response to the particular signal is received in the first state. It is determined that the device supports a configuration mode outside the protocol based on the received response. The configuration mode is entered based on the response. One or more in-band configuration messages are sent within the configuration mode.

In-band configuration mode

Techniques and mechanisms for exchanging single-ended communications with a protocol stack of an integrated circuit package. In an embodiment, an integrated circuit (IC) chip includes a protocol stack comprising a transaction layer which performs operations compatible with a Peripheral Component Interconnect Express&#x2122; (PCIe&#x2122;) specification. Transaction layer packets, exchanged between the transaction layer and a link layer of the protocol stack, are compatible with a PCIe&#x2122; format. In another embodiment, a physical layer of the protocol stack is to couple the IC chip to another IC chip for an exchange of the transaction layer packets via single-ended communications. A packaged device includes both of the IC chips.

Method, apparatus and system for single-ended communication of transaction layer packets

Described is an apparatus which comprises: an amplifier; and a passive continuous-time linear equalizer integrated with a baseline wander (BLW) corrector, wherein the integrated equalizer and BLW corrector is coupled to the amplifier.

Techniques for embedded high speed serial interface methods are described herein. The techniques provide an apparatus for link equalization including an equalization control module to determine at least a first coefficient setting and a second coefficient setting at a remote transmitter based on an algorithm. The apparatus also includes a receiver margining module to determine a first margin value to be associated with the first coefficient setting and a second margin value to be associated with the second coefficient setting. The receiver margining module is to further determine if at least the first margin value is higher than the second margin value.

Link equalization mechanism

Methods and systems to calibrate an on-die resistor relative to an operating voltage of an on-die push-pull driver, and to calibrate the push-pull driver relative to the on-die resistor and relative to operating voltages of the push-pull driver. The calibrated on-die resistor may be used to calibrate receive terminations, a differential transmit termination, and a simulated far-end differential receive termination. The calibrated differential transmit termination and simulated far-end differential receive termination may be coupled in parallel to calibrate current drivers. Calibration of the current drivers may include calibrating voltage swing, and may include a first phase that simultaneously adjusts compensation to the current drivers, and a second phase that individually adjusts the compensation to the current drivers.

Methods and systems to calibrate push-pull drivers

A hand-operated blade sharpener providing engagements of a blade by an abrasive stone at pre-selected angles to the blade is disclosed.

Blade sharpener

A method and system to facilitate configurable input/output (I/O) termination voltage reference in a transmitter or receiver. In one embodiment of the invention, the transmitter and receiver, each has a termination circuit to select a suitable termination reference voltage based on the desired coupling type. In one embodiment of the invention, the transmitter has a termination circuit coupled with a transmission driver and the transmitter selects only one of a supply voltage, a ground voltage and a half supply voltage as a termination voltage reference of the transmission driver. The receiver has a termination circuit to select either a supply voltage or a ground voltage as a termination voltage reference of the receiver.

Method and system to facilitate configurable input/output (I/O) termination voltage reference

A bias circuit includes multiple output legs. During a transition from a low power state to an operational state, multiple output legs are turned on to provide a bias voltage. After a suitable period, at least one of the multiple output legs is turned off.

Driver circuit bias control

In general, the embodiments introduce a pre-charge state between an idle state (when no data in being transmitted) and an active state (when data is being transmitted). In the pre-charge state, both differential signals are pre-charged to the common mode voltage, which is also the crossover voltage. Similarly, an additional pre-charge state is inserted between the active state and the idle state when the signals transition from active to idle. Because both signals for each bit, including the first and last bits, are being driven from the same voltage level, the quality of the first and last bits are improved to be similar in quality to the middle bits.

High speed differential pre-driver using common mode pre-charge

A method for testing a data recovery circuit (DRC) includes disturbing a running variable in a closed control loop of the DRC, as the DRC is processing a received test signal. Data recovered by the DRC, while the DRC was affected by the disturbance, is evaluated.

Testing of integrated circuit receivers

An interface operates at an operating frequency. The interface includes transmitters and receivers that operate within the operating frequency of the interface. The interface also includes circuit elements to allow transmission of signals across the interface in which the signals have a frequency lower than the operating frequency of the interface.

Circuit and method for transferring low frequency signals via high frequency interface

An apparatus and method for low latency power management on a serial data link are described. In one embodiment, the method includes the detection of an electrical idle exit condition during receiver operation in an electrical idle state. Once detected, data synchronization is performed according to one or more received data synchronization training patterns. Finally, when the synchronization is performed within a determined synchronization re-establishment period, the receiver will resume operation according to a normal power state. Accordingly, the embodiment described illustrates an open loop, low latency power resumption operation for power management within 3GIO links.

Apparatus and method for low latency power management on a serial data link

Growing community of inventors

Orangevale, CA, United States of America

Ronald W Swartz