Intel Corporation

Ronald W Silvas

Altug Koker

Joydeep Ray

Prasoonkumar Surti

Ankur N Shah

Abhishek R Appu

Aditya Navale

Jayanth N Rao

Vidhya Krishnan

Murali Ramadoss

Ben J Ashbaugh

John H Feit

Niranjan L Cooray

Changliang Wang

Karol A Szerszen

Gaurav Kumar

Pavan K Lanka

Haichun Dai

Hongbin Ye

A system includes a compression engine that stores the compression format information embedded in the compressed data. The compression format information can be included in a header that includes compression control surface (CCS) information. The system includes a shared memory to store compressed data for multiple hardware pipelines, where blocks of the compressed data have a common memory footprint and the compression header. The compression engine can compress data to store in the shared memory including generation of the header. The compression engine can decompress data read from the shared memory, including identification of the compression format from the header.

Unified stateless compression system for universally consumable compression

Methods, systems and apparatuses may provide for technology that identifies first graphics data that is associated with spatially proximate positions. The technology identifies second graphics data that is associated with spatially proximate positions, and interleaves the first and the second graphics data across a plurality of storage tiles.

Compression and interleaving of spatially proximate data

Examples described herein relate to a system that after decoding of video by the first device, provides a memory address of decoded video in the memory device to a second driver for a second device and perform a second device driver that causes the second device to access the decoded video directly from a translation of the memory address of the memory device, wherein the second device is to access the decoded video with memory properties of the decoded video and decompression information of the decoded video. In some examples, the first device comprises one or more of: a graphics processing unit integrated with a central processing unit (CPU), a discrete graphics processing unit, or a video decoder accelerator. In some examples, the second device comprises one or more of: a graphics processing unit integrated with a central processing unit (CPU) or a discrete graphics processing unit. In some examples, the memory properties of the decoded video comprise swizzle information. In some examples, decompression information of the decoded video comprise a decompression scheme or decompression key.

Processing of data by multiple graphic processing devices

Systems and methods for providing shared virtual memory addressing support for a host system are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations. A memory management unit (MMU) is coupled to the processing resources. The MMU to support a first virtual address size for managing allocation of non-shared virtual memory and to support a second virtual address size for managing allocation of shared virtual memory that is shared between the graphics processor and a host.

Systems and methods in a graphics environment for providing shared virtual memory addressing support for a host system

Embodiments described herein provide an apparatus comprising a processor to allocate a first memory space for data for a graphics workload, the first memory comprising a first plurality of addressable memory locations, allocate a second memory space for compression metadata relating to the data for the graphics workload, the second memory space comprising a second plurality of addressable memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space, and configure a direct memory mapping between the first plurality of addressable memory locations and the second plurality of addressable memory locations. Other embodiments may be described and claimed.

Control surface access using flat memory mapping

A method and system for shared virtual memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a system memory. A CPU virtual address space may be created, and the surface may be mapped to the CPU virtual address space within a CPU page table. The method also includes creating a GPU virtual address space equivalent to the CPU virtual address space, mapping the surface to the GPU virtual address space within a GPU page table, and pinning the surface.

Shared virtual memory

A method for sharing memory between a central processing unit (CPU) and an input/output (I/O) device of a computing device is described. The method may include creating an allocation of memory for the I/O device to operate on. The method includes detecting whether the allocation is not page-aligned, wherein an allocation is page-aligned when its base address and size be evenly divisible by the applicable page-size. The allocation may be successfully shared, even if not page-aligned, even if an operating system of the computing device doesn't support sharing of non-page-aligned allocations.

Growing community of inventors

Sacramento, CA, United States of America

Ronald W Silvas