National Semiconductor Corporation

Ronald W Russell

Daniel D Culmer

Craig N Lambert

Sam S Ochi

James E Solomon

Kyle M Black

A post-assembly trim of a monolithic IC is set forth wherein selected package pins can be employed to address the on-chip trim circuit. Then, after the trim is completed, the circuit is addressed to provide a disconnect of the coupling between the trim pins and the post assembly trim circuit of the IC, while leaving the pins fully usable for other purposes. This means that following the post-assembly trim the trim pins cannot accidentally be employed for further trimming and the packaged IC is user-proof. A circuit that employs zener zapping for both trimming and disconnect is detailed and the invention is clearly usable for plastic encapsulated devices. However, when cavity containing packages are involved it is shown that a combination of zener zapping and fuse blowing can be employed.

User-proof post-assembly offset voltage trim

A JFET operational amplifier input stage is disclosed along with am offset potential trimming circuit. The trimming circuit includes a scaled down compensation stage that is modeled after the input stage and provided with a constant temperature independent bias. This generates a trimming current that varies with temperature inversely with the transconductance of the input stage. A control circuit applies a digitally controlled portion of the trimming current to the input stage so as to compensate the offset potential. The input offset potential is therefore compensated without changing the offset potential temperature drift. Desirably the compensation is achieved after device assembly.

Operational amplifier offset trim that does not change the offset

An expanded analog-to-digital converter includes a first digital-to-analog converter for converting the most significant bits of digital output signal having a given number of bits to a first analog reference signal having a value that is proportional to the value of the most significant bits minus one-half the least significant bit of the digital output signal whenever the value of the most significant bits is other than zero; and a second digital-to-analog converter for converting the least significant bits of the digital output signal to a second analog reference signal. A successive approximation register successively provides the bits of a digital output signal in accordance with a comparison of an analog input signal with the sum of the analog reference signals. A logic circuit coupled to the successive approximation register for providing an indication of whether the value of the most significant bits is other than zero, causes the second analog reference signal to have a value that is proportional to the value of the least significant bits whenever the value of the most significant bits is other than zero, and a value that is proportional to the value of the least significant bits minus one-half the least significant bit of the digital output signal whenever the value of the most significant bits is zero.

Expanded analog-to-digital converter having one-half LSB shift

A pair of transistors are operated at different current densities so as to develop a differential base to emitter potential. This potential is used as a reference in a negative feedback stabilization circuit which passes a current that is regulated by the potential. The circuit can also regulate the currents flowing in a plurality of additional current sources and sinks connected thereto.

Constant current control circuit

An offset adjustment circuit for a differential amplifier includes a current source connected in series with a resistor for establishing a biasing voltage for a pair of field effect transistors (FET) having variable resistors in their biasing circuits. These FET's are connected to introduce currents respective connections between an input stage and a second stage of the differential amplifier. The difference of the currents supplied by the FET's divided by the transconductance of the input stage of the differential amplifier corresponds to an offset which remains fixed with changes in temperature. The offset introduced by the FET's, as determined by the adjusted values of the resistors in their biasing circuits, may be in opposition to the offset of the differential amplifier to either reduce it partially or completely, or it may be additive to the offset of the differential amplifier, as desired.

Offset adjustment circuit

A differential input is applied to four bridge-connected field effect transistors. The bridge drives a differential common base transistor stage. The output can be either differential or single ended as desired taken from the transistor collectors. The circuit provides good common mode rejection and good differential response to signals over a common mode range that exceeds the voltage of the power supply.

Wide common mode range differential amplifier

An output stage for an amplifier operating under capacitive loading conditions includes an FET-bipolar composite connected between its input and its output and an emitter follower connected in parallel with the FET. A current source and current tracking circuit maintains the emitter follower conductive at all times, such that relatively high frequency input signals are supplied to the output through the emitter follower. When the output stage is sourcing current to the load, the signal path is through the emitter follower. When the output stage is sinking current from the load, the signal path is primarily through the FET when relatively low frequency input signals are connected thereto and the signal path is primarily through the emitter follower when relatively high frequency input signals are connected thereto.

Amplifier output stage

An operational amplifier includes an input differential stage formed of a differential pair of transistors, a tail current source supplying that differential pair, and a pair of current source loads, each connected to a respective one of the transistors of the differential pair. A common mode feedback loop is provided from a second stage of the differential amplifier to remove any excess current supplied by the tail current source which is not drawn by the current source loads. A single capacitor is employed for assymetric frequency compensation of the second stage, such that the above described common mode feedback can be applied without producing oscillations.

Differential amplifier

An analog switching circuit employs a field effect transistor as a switching element and a regulation circuit for maintaining the bias on the FET constant with changes in the amplitude of an analog signal in the circuit being controlled. The regulation circuit includes a current source, a pair of elements for generating a voltage drop connected in parallel with one another and in series with the current source, and a circuit for maintaining the voltage drops in those circuit elements equal to one another. The circuit elements are connected in series with one another between the source and the gate of the FET, such that the bias on the FET remains constant. A control circuit is operative to disrupt the balance of currents in the circuit elements to cause the FET to become nonconductive.

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Sunnyvale, CA, United States of America

Ronald W Russell