Trw Limited

Northrop Grumman Systems Corporation

Ronald W Grundbacher

Michael Edward Barsky

Richard Lai

Yaochung Chen

Roger S Tsai

Michael Wojtowicz

Tsung-Pei Chin

Rosie M Dia

Mark Kintis

Po-Hsin Liu

A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.

Fully relaxed channel HEMT device

A process for improving the yield of semiconductors, such as high electron mobility transistors (HEMTs), which are susceptible to damage during conventional metal lift-off techniques. In accordance with an important aspect of the invention, damage to relatively fragile structures, such as submicron dimensioned structures on semiconductors are minimized by utilizing an adhesive tape to peel off undesired metal in close proximity to submicron dimension structures. By using an adhesive tape to peel off undesired metal, damage to submicron dimension structures is minimized thus improving the yield.

Method to separate a metal film from an insulating film in a semiconductor device using adhesive tape

A method of manufacturing a HEMT IC using a citric acid etchant. In order that gates of different sizes may be formed with a single etching step, a citric acid etchant is used which includes potassium citrate, citric acid and hydrogen peroxide. The wafer is first spin coated with a photoresist which is then patterned by optical lithography. The wafer is dipped in the etchant to etch the exposed semiconductor material. Metal electrodes are evaporated onto the wafer and the remaining photoresist is removed with solvent.

Process for forming a large area, high gate current HEMT diode

Partially relaxed channel HEMT device

An enhancement mode FET device ( ) that employs a strained N-doped InAlAs charge shield layer ( ) disposed on an intrinsic InAlAs barrier layer ( ). A gate metal electrode ( ) of the FET device ( ) is controllably diffused through a recess ( ) into the shield layer ( ) to the barrier layer ( ). The resulting enhancement mode device ( ) provides an excellent Schottky barrier with a high barrier height that inhibits undesirable surface depletion effects through charge shielding by the shield layer ( ) in the regions between the recess edge and the gate metal. Minimizing surface depletion effects makes the device more robust by making the surface less sensitive to processing conditions and long-term operation effects.

Enhancement mode device

A single-layer, metal-insulator-metal capacitor, a monolithic microwave integrated circuit including such capacitors, and a process of fabricating such capacitors. The capacitor has a single layer of insulating material between two metallic layers. At least one of the metallic layers has rounded corners, reducing the electric field at the corners, and so lessening the likelihood of breakdown. In one preferred embodiment, each metal layer has rounded corners. The capacitors can be fabricated by an optical lithographic process.

Single-layer dielectric structure with rounded corners, and circuits including such structures

A method for determining the etch depth of a gate recess ( ) in an InP based FET device ( ). The source-drain, current-voltage (I-V) relationship is monitored during the etching process. As the etch depth increases, a kink is formed in the linear portion of the I-V relationship. When the kink current reaches a desired value, the etching is stopped. The kink current is a strong function of etch depth, so small differences in etch depth can be easily targeted. By controlling the etch depth, the characteristics of the transistor can be reproducibly controlled and optimized.

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Hermosa Beach, CA, United States of America

Ronald W Grundbacher