Compaq Computer Corporation, Inc.

Hewlett-packard Development Company, L.p.

Compaq Information Technologies Group, L.p.

Ronald Timothy Horan

Phillip M Jones

Gregory N Santos

Sompong Paul Olarig

Robert A Lester

Robert C Elliott

Stephen R Johnson, Jr

Usha Rajagopalan

John E Theisen

Todd S Behrbaum

Dwight D Riley

Gary W Thome

Gary J Piccirillo

Michael J Collins

Jerome J Johnson

Robert C Elliot

A computer system having at least one central processing unit, system memory, and a core logic capable of accepting an AGP bus is provided with an AGP to AGP bridge connected to the standard AGP bus. The AGP to AGP bridge can accommodate two or more AGP-compatible devices that can be accessed through the standard AGP bus via the AGP to AGP bridge. A PCI to memory bridge is also provided within the AGP to AGP bridge so that PCI devices may be connected to the AGP to AGP bridge. The AGP to AGP bridge is fitted with an overall flow control logic that controls the transfer of data to or from the various AGP devices and the standard AGP bus that is connected to the core logic of the computer system. The AGP to AGP Bridge can utilize a standard 32-bit AGP bus as well as (two) dual 32-bit buses to enhance bandwidth. In an alternate embodiment of the invention, the dual 32-bit buses can be combined to form a single 64-bit bus to increase the available bandwidth. Alternate embodiments of the AGP to AGP Bridge can accommodate the single 64-bit AGP bus for increased performance. Another alternate embodiment can accommodate peer-to-peer transfer of data between AGP busses on the bridge.

Apparatus, method and system for accelerated graphics port bus bridges

A computer system having a highly parallel system architecture with multiple central processing units, multiple core logic chipsets and pooled system memory is provided with one or more AGP ports capable of connection to AGP devices. A memory manager is provided within the operating system for allocating pooled memory resources without regard to the location of that memory. A method is presented for dynamically allocating memory for the AGP device that is located on the same core logic chipset to which the AGP device is connected. By allocating local memory instead of allocating memory on remote core logic units, the AGP device can access the needed memory quickly without memory transmissions along the host bus, thereby increasing overall performance of the computer system.

Method and system for allocating memory from the local memory controller in a highly parallel system architecture (HPSA)

Method and system for allocating AGP/GART memory from the local AGP memory controller in a highly parallel system architecture (HPSA)

A computer system having a core logic chipset that interconnects a processor(s), a system memory and peripheral device agents. The core logic chipset has a programmable memory access arbiter that may be programmed to optimize accesses by the computer system processor(s) and agents to the system memory for best computer system performance. The memory access arbiter may be programmed specifically for each system agent. An access count register may be incorporated into the core logic chipset wherein each system agent may be represented by a portion of the access count register. The values programmed into the portions of the access count register determine how many memory accesses the associated agent may take before another agent is granted a memory access, and how many cachelines may be transferred during a memory access.

Accelerated graphics port programmable memory access arbiter

A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ('AGP') bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ('GART table') is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page.

Graphics address remapping table entry feature flags for customizing the

A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ('AGP') bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ('GART table') is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing. The required amount of virtual memory address space for AGP is determined from the AGP device and the information is put into a register of the core logic so that the computer system software may allocate the required amount of memory and assign a base address thereto during computer system startup or POST.

System and method for dynamically allocating accelerated graphics port

A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ('AGP') bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ('GART table') is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. One of the feature flags is used as a Present Bit for a corresponding memory page. When the feature flag Present Bit is set, the memory page has been reserved in the physical memory for graphics data and an address translation may be carried out. When the feature flag Present Bit is clear, the memory page has not been reserved for graphics data in the physical memory and a determination must then be made whether to perform the translation or generate an error signal to the computer processor.

Generating an error signal when accessing an invalid memory page

A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ('AGP') bus device such as an AGP graphics controller, and a host processor and computer system memory wherein AGP transaction read requests are merged from the AGP graphics controller and retired when these requests are within a cacheline of the memory being accessed. The core logic chipset will request a memory cacheline read as it begins processing a current AGP transaction read request. Once the memory read access is initiated, the transaction read request will be popped off an AGP request queue in order to evaluate the next in order transaction request. If the next request can be partially or completely retired by the memory read access previously started, then the memory access that would have been normally required may be skipped and the data from the previous memory read access is used instead. This AGP read transaction merging may continue until the next in order transaction read request is located in a different cacheline of memory or the original memory request is ready to return data. A memory data buffer may also be utilized to store unused quadwords of the cacheline read from a memory access so that some subsequent AGP transaction requests may be retired without having to access a previously read cacheline of memory.

Accelerated graphics port read transaction merging

A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ('AGP') bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ('GART table') is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory. The core logic chipset may cache a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. When a GART table entry is not found in the cache, a memory access is required to obtained the needed GART table entry. There are two GART table entries in each quadword returned in toggle mode of the cacheline of memory information returned from the memory read access. At least one quadword (two GART table entries) are stored in the cache each time a memory access is required because of a cache miss.

Accelerated graphics port multiple entry gart cache allocation system

A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ('AGP') bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ('GART table') is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. A plurality of AGP memory-mapped status and control registers are stored in the computer system memory, and are used for status and control of AGP functions in the computer system.

Accelerated graphics port memory mapped status and control registers

A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ('AGP') bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect ('RegPCI') bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ('REQ') and Grant ('GNT') signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test ('POST'). Software configuration may also be determined upon detection of either an AGP or a RegPCI device connected to the common AGP/RegPCI bus.

Dual purpose computer bridge interface for accelerated graphics port or

A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ('AGP') bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ('GART table') is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing. The required amount of virtual memory address space for AGP is determined from the AGP device and the information is put into a register of the core logic so that the computer system software may allocate the required amount of memory and assign a base address thereto during computer system startup or POST. An AGP Valid bit is set to indicate whether an AGP device is present or not. If the AGP device is not present, then no virtual memory address space is allocated during the computer system startup.

Valid flag for disabling allocation of accelerated graphics port memory

A core logic chip set is provided in a computer system to provide a bridge between host and memory buses and an accelerated graphics port ('AGP') bus adapted for operation of two AGP devices, or one AGP device and one peripheral component interconnect ('PCI') device. A common AGP bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and the AGP and/or PCI device(s). The core logic chip set has an AGP/PCI arbiter having Request ('REQ') and Grant ('GNT') signal lines for each AGP and/or PCI device connected to the AGP bus. Another embodiment has a plurality of AGP buses for a plurality of AGP devices. This allows concurrent operation for AGP devices connected to different AGP buses. Two of the AGP buses may be combined to connect to one 64 bit PCI device.

Computer bridge interfaces for accelerated graphics port and peripheral

A core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ('AGP') bus and host and memory buses, as a bridge between an additional peripheral component interconnect ('PCI') bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. A common bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and either an AGP or PCI device(s). The core logic chip set also has an AGP/PCI arbiter having additional Request ('REQ') and Grant ('GNT') signal lines so that more than one PCI device may be utilized on the additional PCI bus. Selection of the type of bus bridge (AGP or PCI) in the core logic chip set may be made by a hardware signal input, software during computer system configuration or power on self test ('POST'). Software configuration may also be determined upon detection of either an AGP or PCI device connected to the common bus.

Growing community of inventors

Houston, TX, United States of America

Ronald Timothy Horan