Storage Technology Partners

Ronald Tanizawa

John J Zasio

Dwight Elvey

A VLSI chip tester for defining and performing functional tests, delay tests, and DC parametric tests on VLSI chips. The VLSI chip under test is mounted to a paddle card which, in turn, is detachably held under pressure against a circuit board mounted in a test fixture. A connector is sandwiched between the paddle card and circuit board. The connector has insulated, spaced-apart conductors that are orthogonal to the paddle card and circuit board, and that provide electrical contact between each pin of the VLSI chip under test and a corresponding pad on the circuit board. Shift register circuits mounted to the circuit board provide a single stage corresponding to each I/O pin of the device under test. Each stage may function as an input or output device. A computer or computers are coupled to the shift register circuits through appropriate cabling and driver/receiver/termination circuits. Test data to be sent to or from the computer may be shifted serially into or out of the shift register circuits. Similarly, test data to be sent to or from the device under test may be shifted in parallel into or out of the shift register circuits. A self-test capability is provided.

Growing community of inventors

San Jose, CA, United States of America

Ronald Tanizawa