Cirrus Logic Inc.

Stmicroelectronics Gmbh

Texas Instruments Corporation

Benchmarq Microelectronics, Inc.

Ronald T Taylor

Michael E Runas

Sudhir Sharma

G R Rao

James Leon Worley

William F Davies, Jr

Doran David

George A Giles

A row driver circuit receives a first supply voltage and a second supply voltage. The circuit provides the first supply voltage on an output responsive to the first supply voltage being greater than a threshold value. The circuit generates a boosted voltage that is greater than the first supply voltage and provides that boosted voltage on the output responsive to the first supply voltage being less than the threshold value.

Method and circuit for controlling generation of a boosted voltage in devices receiving dual supply voltages

A memory system includes a first array and a second array of memory cells. The memory system allows for a quick transfer of the contents of one of the arrays with another one of the arrays. Through the use of a transfer gate ( ) interposed between column decoders ( and ) corresponding to the two memory arrays, data may be transferred between the two arrays in a single timing cycle. Furthermore, even given the interconnection between the two memory arrays due to the transfer gate, the two memory arrays can be operated independently of one another, with respect to address, data, and timing information.

Method and apparatus for transferring data in a dual port memory

A processing system 100 is disclosed which includes a system master 101, a system bus 102 coupled to the master, and a plurality of bus interface circuits 106 coupled to bus 102. A first one of the bus interfaces 106 includes a mapping signal input coupled to the master and a mapping signal output, the first bus interface 106 operable to latch-in at least one first selected address bit presented by the master on the system bus in response to a mapping enable signal received at the mapping signal input from the master 101. A second bus interface 106 is provided coupled to the bus 102 and having a mapping signal input coupled to the mapping signal output of first bus interface 106, the second bus interface 106 operable to latch-in at least one second selected address bit presented by the master 101 on the bus 102 in response to a second mapping enable signal received at the mapping input of the second bus interface 106 from the first bus interface 106.

Circuits, systems and methods for memory mapping and display control

An information processing system 400 includes a subsystem 402 having a processing resource 404 and a bus interface 403. An active logic mapping signal is presented to a mapping input bus interface 403. The system also includes a master processing device which is operable to write at least some bits of a starting address into bus interface 403, determine an ending address for subsystem 402 and lock subsystem 402.

Circuits, systems and method for address mapping

A method of stress testing a DRAM such that higher voltages of up to the supply voltage VDD may be applied to the oxide of memory cell capacitors. The DRAM is driven into a stress test mode when the sense amplifiers have been isolated, the precharge voltage and the half bitlines have been grounded, and the word line boost circuitry has been disabled or set to operate at a lower voltage level. These conditions allow the memory cell capacitors, isolated from the sense amplifiers and the word line boost circuitry, to be stress tested independently at a lower power supply and word line voltage levels than are used to stress test conventional DRAMs. The memory cell oxide stresses are applied at room temperature, in wafer form, in seconds instead of hours, and before the configuration of redundancy elements. The inventive method permits the critical burn-in VDD value to be chosen so as to optimize burn-in of the memory cell capacitors and peripheral CMOS circuitry.

Method for stress testing the memory cell oxide of a DRAM capacitor

This invention is a method for boosting the voltage level of a wordline in a DRAM having bitlines, sense amplifiers, isolation devices, bitline loads, an X decoder device and a Y select device. In the preferred method, when the wordline level reaches VDD, the decoder is disabled causing the wordline to stay at the VDD level. The sensing amplifier is also caused to be isolated so as to allow the wordline voltage to track the bitline voltage through capacitive coupling across the access MOSFET of the memory cell being read or written to. As a result, the wordline voltage is increased to a supervoltage as the bitline voltage increases. After the supervoltage is reached on the wordline, the sensing amplifier is connected causing feedback from the amplifier to drive the wordline voltage toward the VDD level and the disabled bit toward GND during this time. At the end of the wordline clock signal, the voltage is at GND and each of the bitlines are returned to their neutral mid-voltage level.

Self boosted wordline

A display control system (200) for transferring video and graphical data processed in a first processing device (201) having a dedicated display screen to a second processing device (202) for display on the screen (152) of a conventional television set (150). The first processing device (201) and the second processing device (202) communicate by means of a pair of optical driver/receivers (203, 207). The second processing device (202) captures selected frames from a broadcast television picture displayed on the screen (152) of the television (150) and transmits the captured frames to the first processing device (201) for storage or display on the dedicated display screen.

Multi-media processing system with wireless communication to a remote

A sense amplifier sensing data on a pair of complimentary half-bitlines 301a, 301b connected to a static random access memory cell 300. First and second sensing transistors 405a, 405b amplify a voltage difference between first and second half-bitlines 301 during an active cycle. First and second restore transistors 404a, 404b pull the first and second half-bitlines to corresponding first and second voltage rails in response to the amplified voltage difference. SR Latch 406, 407 retains data from cycle to cycle.

Circuitry and methods for dynamically sensing of data in a static random

A system is provided for transferring information across a conductor 203. Transmitting circuitry 210 receives information in the form of a first signal having a first voltage swing and, in response, outputs a second signal having a second voltage swing. The first voltage swing is between a first high voltage and a first low voltage and the second voltage swing is between a second high voltage less than the first high voltage and a second low voltage greater than the first low voltage. The second high voltage is substantially equal to a voltage level of a first voltage rail to which the transmitting circuitry 210 is coupled and the second low voltage is substantially equal to a voltage level of a second voltage rail to which the transmitting circuitry 210 is coupled. The conductor 203 carries the second signal output from the transmitting circuitry 210. Receiving circuitry 212 receives the second signal output from the transmitting circuitry 210 via the conductor 203 and, in response, outputs a signal having the first voltage swing.

Circuits systems and methods for reducing power loss during transfer of

A memory 20 includes a first array 100 and a second array 102 of memory cells. A first data port 118 allows for the exchange of data with the first array 100 and a second data port 120 allows for the exchange of data with the second array 102. Memory system 20 also includes a circuitry 122 for controlling data exchanges in a selected mode with the first array 100 via the first data port 118 and with the second array 102 via the second data port 120, the exchanges with the first and second arrays 100 and 102 being asynchronous.

Dual port memories and systems and methods using the same

A memory 600 including an array of memory cells 201 and a plurality of input/output terminals 220 for receiving control bits during control cycles and accessing selected ones of the cells 201 during data access cycles. A command bit input terminal 221 is provided for receiving command bits for initiating the control cycles and a mapping input terminal 222 is provided for receiving a mapping enable signal to initiate a mapping mode. Circuitry 215/ 216 is provided for decoding control bits received during at least one control cycle occurring during a mapping mode for allowing a mapping of a set of addresses for accessing the cells of the array 201.

Memory system with multiplexed input-output port and memory mapping

A memory including a plurality of input/output terminals 220 for exchanging data bits during a data access cycle and receiving command and control bits during a command and control cycle. The memory further includes an array of memory cells 201, a data input/output circuitry for transferring data between the input/output terminals and the array of memory cells during the data access cycle, and control circuitry for controlling operations of the memory in response to command and control bits received at the input/output terminals during the command and control cycle.

Memory system with multiplexed input-output port and systems and methods

A system 500 is provided for transferring signals across a bus which includes a power source 550 operating between a high voltage rail at a first supply voltage level and a low voltage rail at a second supply voltage rail, power source 550 generating a third supply voltage level on an output thereto. The third supply voltage level is greater than the first supply voltage level. A processing circuitry 103, 104 is included for generating a plurality of data signals each having a first voltage swing between a first logic high level substantially equal to the first supply voltage level and a first logic low level substantially equal to the second supply voltage level. The system additionally includes a plurality of buffers, 520, each buffer 520 being coupled to the power source 550 output and receiving a selected one of the data signals. Each buffer 520 generates a boosted drive signal having a second voltage swing between a second logic high level substantially equal to the third supply voltage level and a second logic low level substantially equal to the second supply voltage level.

Circuits, systems and methods for transferring data across a conductive

A system 600 is provided having a line driver 202 for transmitting signals across a line 201 from a first processing circuit 601 to a second processing circuit 602. Line driver 202 receives an input signal from processing circuit 601 having a first voltage swing between a first high voltage level and a first low voltage level. Line driver 202 reduces power dissipation in line 201 by transmitting an output signal on line 201 having a second voltage swing between a second low voltage level greater than the first low voltage level and a second high voltage level less than the first high voltage level. System 600 also contains comparator 610 which receives the signal having the reduced second voltage swing and compares the received signal to a reference voltage. The output of comparator 610 restores the received signal to the full voltage swing of the input signal received by line driver 202 and transfers the restored signal to processing circuit 602.

Growing community of inventors

Grapevine, TX, United States of America

Ronald T Taylor