International Business Machines Corporation

Ronald S Svec

Dennis P Cheney

Eric M Foster

William Robert Lee

Chuck Hong Ngai

Eric Eugene Retter

David Allen Hrusecky

Lawrence D Curley

Charles John Stein

Francesco A Campisano

Leland D Richardson

Bryan J Lloyd

Agnes Yee Ngai

Adrian Stephen Butter

Jeffery Dean Carr

Steven Bradford Herndon

Daniel J Buerkle

Hugh C Holland

Robert J Kammerer

A digital video decoder system, method and article of manufacture are provided having integrated scaling capabilities for presentation of video in full size or a predetermined reduced size, while at the same time allowing for reduced external memory requirements for frame buffer storage. The integrated system utilizes an existing decimation unit to scale the decoded stream of video data when the system is in scaled video mode. Display mode switch logic oversees switching between normal video mode and scaled video mode, wherein the switching occurs without perceptual degradation of a display of the decoded stream of video data. Scaled decoded video frames are buffered in a frame buffer which is partitioned depending upon whether the digital video decoding system is in normal video mode or scaled video mode. In scaled video mode, the frame buffer accommodates both full size I and P frames, as well as scaled I, P & B frames. The full size I and P frames are used to support future decode operations, while the scaled I, P & B frames are retrieved for display.

MPEG video decoder with integrated scaling and display functions

A method and structure for dynamically blocking access of a request signal R to a shared bus such that R originates from a non real-time master and requests access to an address range of an address space. The shared bus manages requests for access to the address space. The non real-time master and a real-time master compete for access to the address space by presenting address access requests to the shared bus. The dynamic blocking of access by R to the shared bus is accomplished by use of a request limiter, which is a device that is coupled to a real-time clock and uses an algorithm to determine when to enable and disable access of R to the shared bus. The algorithm uses a windowing scheme that permits access of R to the shared bus every N clock cycle, wherein the value of the integer N may be supplied to the request limiter by the real-time master. An example of the algorithm includes blocking access of R to the shared bus whenever all of the following conditions occur: the real-time master has a non-empty internal queue, the real master and the non real master are both requesting access to a same address range of the address space, and the real-time clock is not at the N clock cycle that permits access of R to the shared bus.

Pre-arbitration request limiter for an integrated multi-master bus system

A technique for transferring data between a first device and a second device using a shared line buffer connected to a system bus which couples the first device and the second device. The technique includes (i) transferring data between the line buffer and dedicated memory associated with the first device, wherein the first device includes a data controller coupled to the system bus through a bus interface. The transferring (i) includes using the data transfer controller to effectuate a multiword data transfer between the dedicated memory and the line buffer. The technique further includes multiword data (ii) transferring between the line buffer and the second device across the system bus. When the transferring (i) precedes the transferring (ii), data is read from the dedicated memory from output to the second device, and when the transferring (ii) precedes the transferring (i), data is written to dedicated memory from the second device.

High bandwidth data transfer employing a multi-mode, shared line buffer

An integrated digital video system is configured to implement picture-in-picture merging of video signals from two or more video sources, as well as selective overlaying of on-screen display graphics onto the resultant merged signal. The picture-in-picture signal is produced for display by a television system otherwise lacking picture-in-picture capability. The digital video system can be implemented, for example, as an integrated decode system within a digital video set-top box or a digital video disc player. In one implementation, a decompressed digital video signal is downscaled and merged with an uncompressed video signal to produce the multi-screen display. The uncompressed video signal can comprise either analog or digital video. OSD graphics can be combined within the integrated system with the resultant multi-screen display or only with a received uncompressed analog video signal.

Integrated video processing system having multiple video sources and implementing picture-in-picture with on-screen display graphics

A programmable bi-directional external graphics/video (EGV) port for a video decode system chip having a video decoder and an internal digital display generator circuit is provided. The programmable EGV port employs a fixed number of signal input/output (I/O) pins on the video decode system chip while providing a plurality of connection configurations for an external graphics controller, an external digital display generator circuit and an external digital multi-standard decoder to the video decoder or the internal digital display generator circuit of the chip. The EGV port includes receiver/driver circuitry for accommodating in parallel a plurality of input/output signals, including pixel data signals and corresponding synchronization signals, as well as a programmable port controller adapted to be coupled between the receiver/driver circuitry and an internal bus of the video decode system allowing access to at least one of the video decoder and the internal digital display generator circuit. The programmable port controller is programmable to either receive data into the video decode system chip or to send data out from the video decode system chip.

Programmable external graphics/video port for digital video decode system chip

A method and system of operating a digital data decoder. In accordance with this method, a first stream of encoded data is transmitted to the decoder, and a second stream of encoded data is stored in a memory device. One of the first and second streams of encoded data is selected, and the decoder is used to decode that selected stream of encoded data. This second stream of data could have been placed in the memory device by other devices or processes present in an STB system. In this case, all the decoder needs to process the data is a pointer to it and some additional information about, for example, its size. Since the processor has access to all memory, it can do any necessary parsing/manipulation required by the stream format. This provides a large degree of flexibility in this area. The processor can then pass location and attributes of data to the decoder. This also minimizes data movement to/from memory, reducing bandwidth requirements.

Method to play audio and video clips through MPEG decoders

Method, system and computer program product are provided for selectively separately updating multiple system time clocks or synchronously updating the multiple system time clocks (STCs). Separate or simultaneous updating of the system time clocks is attained by selectively adjusting the addresses to the system time clocks in updatable address register fields. A first address value is provided to a first address register associated with a first STC register and a second address value is provided to a second address register associated with a second STC register. Independent updating of the first STC register and the second STC register is performed when the first address value and the second address value are different, while synchronous updating is performed when the first address value and the second address value comprise a common address value. The technique can be extrapolated to any number of clocks to be updated.

Method and system for selectively independently or simultaneously

An MPEG digital video decoder system, method and computer program product are presented for monitoring decoding of an encoded digital video signal for one or more predefined illegal conditions. Error detection logic is coupled to the variable length (VLC) decoder, inverse quantizer (IQ), inverse discrete cosine transformer (IDCT) and motion compensator (MC) of the decoder for detecting an illegal condition within at least one of the VLC decoder, IQ, IDCT and MC during decoding of the encoded digital video signal. The monitored illegal conditions can include a VLC/IQ control error, an IQ level overrun, and IQ/IDCT buffer error, an MC idle error and an MC macroblock start error. Error signals are reported to a central error register which is monitored periodically by the decoder's control processor. The control processor initiates recovery within the decoder system prior to stoppage of the system due to the illegal condition.

Early error detection within an MPEG decoder

A method of and apparatus for identifying a Dual Prime motion estimation best match and generating motion vectors pertaining thereto for inter-picture video compression in a motion picture having images of F.sub.1 and F.sub.2 parities. The Dual Prime method of motion estimation described herein includes a method of generating motion vectors. The motion vectors point from a macroblock in a current field to a macroblock in a past field for inter-picture video compression in a motion picture having images of F.sub.1 and F.sub.2 parities. The first step in the method is defining a macroblock in a parity field of the current picture. Next, the preceding field of the same or opposite parity is searched to find a first best match macroblock in the preceding field. Once a best match macroblock is found, a vector is formed from the current macroblock in the current parity field to the first best match macroblock in the preceding parity field. This vector is scaled so that it refers to a second dual prime macroblock in the opposite parity field, that is the parity field of opposite parity with respect to the first best match macroblock which defines the center of a dual prime search window. Then, the average of the first best match macroblock and the set of second dual prime macroblocks in the dual prime search window is taken and the search window is searched to determine the best match dual prime macroblock. The search is typically conducted at half pixel locations inside a one square pixel dual prime search window. The appropriate dual prime motion vector and differential motion vector (dmv) are formed. These are motion vectors which point to both the first best match macroblock and the best match dual prime macroblock.

Dual prime motion estimation system and method

Disclosed is a method of forming a bidirectionally coded picture, i.e., a B frame, from two reference pictures, e.g. I or P frame pictures. The method utilizes a single memory fetch of each reference picture, and interpolation of the estimated motion of each picture. This is accomplished by identifying a full pixel closest match from three full pixel boundary searches, calculating half pixel reference picture data therefrom, interpolating the half pixels to form bidirectionally coded pictures, and finding the closest match at the half pixel boundary. The intermediate results are stored in an 18.times.18.times.11 bit buffer holding a 7 bit partial sum for each pixel, said partial sum formed by adding the six most significant bits of corresponding I and P frame pixels. In this buffer four bits of each word in the buffer are the two Least Significant Bits of the corresponding I and P frame pixels.

Half pel motion estimation method for B pictures

A device information interface for a channel to channel I/O device having a plurality of channel adapters. A device interface bus interconnects each of the channel adapters, permitting an exchange of data between channel adapters. A virtual device storage array at each channel adapter stores the status of inactive channel devices associated with a connected channel. Inquiries as to the status of a logical adapter may be sent over the device interface bus. Logic circuits at the receiving adapter will decode the inquiry and address the virtual storage array to obtain the status of the logical adapter for forwarding over the bus to the inquiring adapter.

Growing community of inventors

Berkshire, NY, United States of America

Ronald S Svec