Intel Corporation

National Semiconductor Corporation

Xlnt Designs, Inc.

Tele Digital Development, Inc.

Ronald S Perloff

Fazil Ismet Osman

James R Hamstra

Robert M Grow

Louise Y Yeung

Timothy L Garverick

Gabriel M Li

Christopher H Bracken

John S Bell

Anderson H Frederik

Roger S Moyers

Thrysoee J Christian

Sally Cordes

Lawrence J Pollack

Ramiro Calvo

Michael F Harris

A method of communicating frames of management information includes loading a frame of management information from one of a plurality of stations into a respective one of a plurality of buffers. Whether the frame contains more than a predetermined number of bytes is determined. If an end of the frame is loaded into the respective one of the buffers, then a frame presence flag associated with said one of the plurality of stations is set. A request signal is transmitted to a station management module if the frame contains more than the predetermined number of bytes or if the buffer already contains management information associated with a previously loaded frame. The plurality of stations is polled to determine whether respective frame presence flags have been set. A buffer reading process is performed in a manner dependent upon whether the buffer reading process was triggered by one of the frame presence flags or by the request signal, to provide the station management module with the management information in the frame.

Communication system and method for communicating frames of management information in a multi-station network

The invention relates to multi-device link aggregation (MDLA). A first MDLA device is connected to a second MDLA device by an MDLA internal link. Each of the interconnected first and second MDLA devices is connected to at least one common link aggregation (LAG) partner device by an aggregated link, respectively. Typically, the first and second MDLA devices exchange protocol data units (PDUs) to detect devices that are connected to both the first and second MDLA devices such that they are able to trick the detected devices into behaving as though the two MDLA devices are a single device. If one of the MDLA devices fails, traffic of the associated aggregated link to the failed MDLA device can be automatically forwarded by the other non-failed MDLA device.

Multi-device link aggregation

To maintain order in a pipelined process, a number of memory locations of a result memory are sequentially reserved for a number of processes as the processes are sequentially dispatched for execution. As an integral part of the sequential reservation, validity determination facilitators to be subsequently employed to correspondingly facilitate determining whether valid processing results of said processes have been stored into corresponding ones of said reserved memory locations are also pre-determined. Additionally, the reserved memory locations are sequentially read to sequentially accept the processing results in order. Each value read from a reserved memory location is accepted only if the corresponding validity determination facilitator exhibits a predetermined relationship with a corresponding validity determination reference value. The validity determination reference values are complementarily maintained and integrally obtained through the sequential read process.

Method and apparatus for maintaining order in a pipelined process and its application

An apparatus is provided with a first and a second first in, first out storage structure (FIFO) that are correspondingly associated with a first and a second resource. The apparatus is further provided with first and second control logic correspondingly coupled to the first and the second FIFO to write a first and a second control value into a first and a second current write storage location of the first and the second FIFO respectively when the first resource is assigned with a first task. The first and second control logic further write the second and the first control value into a third and a fourth current write storage location of the first and the second FIFO respectively when the second resource is assigned with a second task. Together, the elements enable the resources to cooperatively generate results for the sink process.

Method and apparatus for coordinating cooperating resources and its application

A hash CAM is provided with a first and a second memory array, and comparison circuitry. The first memory array is used to store an m-bit input in a partitioned manner suitable for being subsequently output in a successive manner in portions of size m/p, where m and p are positive integers, with m being greater than or equal to p. The second memory array is used to store a plurality of threaded lists of entries, with each entry having a comparand also m-bit in size and stored in the same partitioned manner suitable for being selectively output in the same successive manner in portions of size m/p. The successive output is made responsive to an n-bit index generated in accordance with the m-bit input, with n being also a positive integer, but smaller than m. The comparison circuitry, which is complementarily reduced in width, is used to successively compare corresponding portions of the m-bit input and the selectively output comparand(s) to cumulatively determine if the m-bit input relates to one of the output comparands in a predetermined manner. In each of a number of applications, a look-up engine is provided with the hash CAM. In one particular application, a forwarding section of a networking device is provided with such look-up engine.

Hash CAM having a reduced width comparison circuitry and its application

A hash CAM is provided with a hashing unit and a memory array. The hashing unit is designed to generate an n-bit index in response to an m-bit input, where n and m are positive integers, and n is smaller than m. The memory array is designed to store a number of truncated comparands of size r (in units of bits), and to output a selected one of the stored truncated comparands in accordance with the n-bit index, for comparison with a subset of r selected bits of the m-bit input, where r is also a positive integer, and m&minus;r is less than or equal to n. In each of a number of applications, a look-up engine is provided with the hash CAM. In one particular application, a forwarding section of a networking device is provided with such look-up engine.

Hash Cam having a reduced size memory array and its application

A FIFO storage structure is provided with a RAM array including a number of memory locations, and control circuitry coupled to the RAM array. The control circuitry facilitates sequential write and read accesses of the memory locations, as well as non-sequential re-read of previously read memory locations. The control circuitry includes in particular circuit elements for facilitating variably deferred release and reclaiming of sequentially read in-use ones of the memory locations, thereby allowing the non-sequential re-reads to be performed in addition to the fundamentally sequential writes and reads. In each of a number of applications, a look up engine is provided with the enhanced FIFO. In one particular application, a forwarding section of a networking device is provided with such look up engine.

FIFO with random re-read support and its application

A method and apparatus for coupling a signal from one node to another node prepares a signal for transmission, performs error checking on such signal while simultaneously transferring such signal within a transmitting node, transmits the signal from the transmitting node, receives and formats the signal at a receiving node, including an identifying portion and a data portion, and directly stores the data portion in memory that is directly accessible by a user process executing in the receiving node while simultaneously performing error checking.

Method and apparatus for assisting data bus transfer protocol

A high performance bus and bus interface device for interconnecting numerous devices without using dedicated high current drivers at each device. The bus is synchronous and divided into a plurality of primary local busses and at least one global bus. Data can be transferred from a first device over a first primary local bus through a first global transceiver, over the global bus to a second global transceiver, and then to a second device through a second primary local bus. The bus is driven to a known state at the end of each burst of data transmitted by a device, before the bus is relinquished to another device. Buffers are provided in each device on the primary local bus which can be accessed by other devices. Buffer management includes: (1) determination by each transmitting device of buffer availability at each receiving device; (2) 'claiming' use by the transmitting device of a buffer in the receiving device for transfers from the transmitting device, including locking out other devices from writing to that buffer; (3) capability of the transmitting device to move received data to the buffer in the receiver; and (4) notification to all devices that the transfer is complete. The bus is used to transfer data between ports of a LAN bridge or switch. A dedicated lookup bus allows address lookup logic to be accessed without arbitrating for the data bus. A distributed CAM is used to perform address lookup functions.

Synchronous bus and bus interface device

Ring network security system with encoding of data entering a subnetwork

Systems and methods for providing graceful insertion of a station or tree into a ring type network. According to one aspect of the invention, graceful insertion is achieved after coupling a tree to a tree link of a master port by switching the tree into a local ring, holding the local ring, and awaiting a token on the network ring. After a token is received on the network ring, the tree is switched from the local ring to the network ring. Monitoring ring status in hardware provides the responsiveness necessary which software graceful insertion typically cannot provide.

Graceful insertion of a tree into a ring network

A network station's elasticity buffer includes a memory core together with write and read pointer logic. The memory core includes a START area and a CONTINUATION area which is a cyclic buffer. Under normal conditions, the read pointer follows the write pointer cyclically in the CONTINUATION area. However, upon detection of a start delimiter or upon station reset, the pointers recenter to the START area. Separate synchronizing logic is provided for each of the two recentering modes to reduce metastability problems caused by asynchronous sampling of data. A delay-by-one mechanism is built into the start delimiter mode synchronization scheme so that, under certain conditions, the read pointer is held in the CONTINUATION area for an additional read so an early sample of the read-start signal by the station's local clock while the read pointer is well behind the write pointer will not drop the last character of the previous frame when that frame is not separated from the next start delimiter by a sufficient interframe gap. A look-ahead-look-current detector insures that the there is not too much initial separation between the write pointer and the read pointer. A delay-GO mechanism is built into the reset mode synchronization scheme to prevent irregular dropping of line state characters when the local byte clock is trapped within the metastability window while clock drift is infinitesimal. The read pointer logic also includes a mechanism for preventing the delay-GO mechanism from creating too much initial separation between the write pointer and the read pointer.

Byte-wide elasticity buffer

In an FDDI token ring network, a repeat filter that treats FDDI Set and Reset symbols occurring in a frame prior to an End Delimiter symbol as a violation and does not repeat these symbols onto the FDDI ring. In addition to the three states described in the FDDI repeat filter standard for a byte-wide implementation, a repeat filter in accordance with the present invention includes a fourth END state. The presence of this END state allows the REPEAT state to be restricted such that it treats bytes within a frame with either symbol of the byte being either a Set or Reset symbol as a violation and a Halt byte is transmitted onto the ring; the repeat filter then enters the Halt state. In addition, the repeat filter is also responsive to 'mixed' bytes that consist of an FDDI data symbol and an FDDI control symbol. If the mixed byte is a data symbol followed by an End Delimiter symbol, then the repeat filter transmits an FDDI zero symbol followed by an End Delimiter symbol and enters the END state; if the mixed byte consists of a data symbol followed by an Idle symbol, then the repeat filter transmits an Idle byte and enters the Idle state.

Byte-wide repeat filter

A pattern injector for testing stations in a data communications network and the physical link between them. The pattern injector replaces normal characters in a normal, unmodified stream with injection characters. The pattern injector includes a multiplexor that receives both a current normal character and the injection character as inputs and provides the injection character as its output upon receipt of a select signal. Selection logic responsive to mode selection inputs selectively provides the select signal to the multiplexor in response to the various programmable pattern injector modes. In the Off mode, no replacement of normal characters occurs. In the One-Shot mode, the n.sup.th normal character after detection of a preselected normal character in the unmodified stream is replaced with the injection character. In the Periodic mode, every n.sup.th normal character in the unmodified stream is replaced with the injection character. In the Continuous mode, all normal characters in the unmodified stream are replaced with the injection character.

Pattern injector

Apparatus and methods for encoding information characters received by a station from a transmission medium to generate internal code points for retrieval or retransmission by the station. The encoding provides an internal symbol set that is able to pass complete line state information via its internal code points, thereby eliminating the need for extra signals to indicate the current line state. The code points can also report error situations, such as elasticity buffer errors, and can be accepted by the station's transmitter to be encoded and, after appropriate filtering, repeated onto the transmission medium. The internal code points are optimized so that the code point set minimizes the decoding logic at the receiving end, be it the station's Media Access Control function or its transmitter. Furthermore, internally, the station may make use of the internal code points to synchronize the receiver elasticity buffer.

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Poway, CA, United States of America

Ronald S Perloff