IP Reservoir, LLC

Washington University

Exegy Incorporated

Q-net Security, Inc.

Other

Magtek, Inc.

Ronald S Indeck

Mark Allen Franklin

Ron Kaplan Cytron

David E Taylor

Roger Dean Chamberlain

David Mark Indeck

Naveen Singla

Jason R White

Marcel W Muller

Sharath R Cholleti

Scott Parsons

Jerome R Cox, Jr

George Lawrence Engel

Alan L Hege

Robert E Morley, Jr

William Berndt Parkinson

Brandon Parks Thurmon

Annmarie D Hart

Lawrence R Meyers

Edward J Richter

Joseph A O'Sullivan

Benjamin Curry Brodie

Nathaniel Sutton McVicar

Justin Ryan Thiel

Carlos Hernandez

Various techniques are disclosed for offloading the processing of data packets that contain financial market data. For example, data packets that contain financial market data can be processed through an offload processor deployed in a network element of a data distribution network to link the data packets with appropriate parsing metadata for the data packets. The network element can be an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform.

Offload processing of data packets containing financial market data

Various techniques are disclosed for offloading the processing of data packets. For example, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform. The data packets processed through the intelligent switch can be unreliable datagram protocol (UDP) data packets from multiple feeds of financial market data, and the offloaded processing can include line arbitration, gap detection, and/or gap mitigation of redundant copies of UDP data packets from one or more financial market data feeds.

Intelligent packet switch

In one embodiment, data at rest is securely stored. A data safe performing data plane processing operations in response to requests of received read data requests, received write data requests, and received read information responses, with the data safe being immutable to processing-related modifications resulting from said performing data plane processing operations. In one embodiment, performing these data plane processing operations does not expose any pilot keys outside the data safe in clear form nor in encrypted form. The pilot keys are used to encrypt information that is subsequently stored in a storage system. One embodiment uses pilot keys to encrypt data that is subsequently stored in a storage system. One embodiment uses data cryptographic keys to encrypt data, uses the pilot keys to cryptographically-wrap (encrypt) the data cryptographic keys, and stores the cryptographically wrapped data keys and encrypted data in a storage system.

Enhanced securing of data at rest

In one embodiment, data at rest is securely stored. A data safe performing data plane processing operations in response to requests of received read data requests, received write data requests, and received read information responses, with the data safe being immutable to processing-related modifications resulting from said performing data plane processing operations. Performing these data plane processing operations does not expose any pilot keys outside the data safe in plaintext form nor in encrypted form. The pilot keys are used to encrypt information that is subsequently stored in a storage system. In one embodiment, the information encrypted and decrypted by the data safe includes data structure instances including feature-preserving encrypted entries generated using feature-preserving encryption on corresponding plaintext data items. In one embodiment, a data vault performs queries on the data structure instances including feature-preserving encrypted entries after retrieval from storage and decryption by the data safe.

Enhanced securing and secured processing of data at rest

Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams.

Method and system for accelerated stream processing

Disclosed herein are methods and systems for integrating an enterprise's structured and unstructured data to provide users and enterprise applications with efficient and intelligent access to that data. In accordance with exemplary embodiments, the generation of feature vectors about unstructured data can be hardware-accelerated by processing streaming unstructured data through a reconfigurable logic device, a graphics processor unit (GPU), or chip multi-processor (CMP) to determine features that can aid clustering of similar data objects.

Method and system for high performance integration, processing and searching of structured and unstructured data

Various techniques are disclosed for offloading the processing of data packets. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize data from the data packets in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform.

Intelligent switch for processing financial market data

A feature extractor for a convolutional neural network (CNN) is disclosed, wherein the feature extractor is deployed on a member of the group consisting of (1) a reconfigurable logic device, (2) a graphics processing unit (GPU), and (3) a chip multi-processor (CMP). A processing pipeline can be implemented on the member, where the processing pipeline implements a plurality convolution layers for the CNN, wherein each of a plurality of the convolutional layers comprises (1) a convolution stage that convolves first data with second data if activated and (2) a sub-sampling stage that performs a member of the group consisting of (i) a max pooling operation, (ii) an averaging operation, and (iii) a sampling operation on data received thereby if activated. The processing pipeline can be controllable with respect to which of the convolution stages are activated/deactivated and which of the sub-sampling stages are activated/deactivated when processing streaming data through the processing pipeline. The deactivated convolution and sub-sampling stages can remain instantiated within the processing pipeline but act as pass-throughs when deactivated. The processing pipeline performs feature vector extraction on the streaming data using the activated convolution stages and the activated sub-sampling stages.

Method and apparatus for hardware-accelerated machine learning

A system is disclosed that comprises a field programmable gate array (FPGA), a network interface, and hardware description code, wherein the hardware description code is compilable into a plurality of bit configuration files for loading onto the FPGA, wherein each bit configuration file defines a pipelined processing operation for a hardware template. The FPGA comprises configurable hardware logic, and the FPGA can be accessible over a network via the network interface for commanding the FPGA to load a bit configuration file from among the bit configuration files onto the FPGA to thereby configure hardware logic on the FPGA to perform the pipelined processing operation defined by the loaded bit configuration file, and wherein the FPGA is configured to (1) receive streaming data and (2) process the streaming data through the configured hardware logic to perform the pipelined processing operation defined by the loaded bit configuration file on the streaming data.

Intelligent data storage and processing using FPGA devices

Various techniques are disclosed for offloading the processing of data packets that contain financial market data. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize financial market data in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform.

A system is disclosed that comprises a field programmable gate array (FPGA), a network interface, and a plurality of hardware templates. The FPGA comprises configurable hardware logic, and the hardware templates define a plurality of different pipelined processing operations. The FPGA can be accessible over a network via the network interface for commanding the FPGA to load a hardware template from among the hardware templates onto the FPGA to thereby configure hardware logic on the FPGA to perform the pipelined processing operation defined by the loaded hardware template, and wherein the FPGA is configured to (1) receive streaming data and (2) process the streaming data through the configured hardware logic to perform the pipelined processing operation defined by the loaded hardware template on the streaming data.

A method and apparatus use hardware logic deployed on a reconfigurable logic device to process a stream of financial information at hardware speeds. The hardware logic can be configured to perform data reduction operations on the financial information stream. Examples of such data reductions operations include data processing operations to compute a latest stock price, a minimum stock price, and a maximum stock price.

Growing community of inventors

St. Louis, MO, United States of America

Ronald S Indeck