International Business Machines Corporation

Siemens Aktiengesellschaft

Ronald R Uttecht

Erick G Walton

Robert Michael Geffken

Richard A Gilmour

William Thomas Motsiff

Rosemary A Previti-Kelly

David C Thomas

Thomas J Hartswick

Jens G Pohl

Vincent James McGahay

Eric Jeffrey White

Stephan Alan Cohen

Stephen G Starr

Albert J Gregoritsch, Jr

Donna J Clodgo

Sheldon C Rieley

Francis E Froebel

Harold W Conru

John Edward Cronin

James Gardner Ryan

Carter W Kaanta

Andrew J Watts

William H Guthrie

Paul A Farrar, Sr

Insulator for integrated circuits and process

The preferred embodiment of the present invention provides a structure and method for personalizing a semiconductor device in the context of a bump array connection to packaging, substrates and such. The preferred embodiment method uses a plurality of conduction lines on said semiconductor device, including a plurality of landing lines and personalization lines. Vias are opened to the plurality of landing lines and selectively opened to a portion of the personalization lines. Connections are made between the opened personalization lines with bumps deposited as part of the bump array.

Semi-conductor personalization structure and method

A shortened fuse link is disclosed. The fuse link comprises a first and second interconnect, with interconnects each being substantially longer than deep. The interconnects are disposed toward each other with a insulator region between them. A fusible conductor, spanning the insulator region, is attached at the top of the interconnects. The present device allows the length of the fusible conductor to be shortened, and results in a fuse link that can be consistently blown with a single laser pulse. Additionally, the fuse link can be used in a staggered layout. The staggered layout of parallel fuse links allows a high number of links in a relatively small area, with or without the use of tungsten barriers, and allows accessing all fuse links through a single fuse blow window.

Fusible links formed on interconnects which are at least twice as long

Personalization structure for semiconductor devices

A semiconductor interconnection consists of a corrosion resistant integrated fuse and Controlled, Collapse Chip Connection (C4) structure for the planar copper Back End of Line (BEOL). Non copper fuse material is directly connected to copper wiring.

Integrated pad and fuse structure for planar copper metallurgy

The fuse link includes a first and second interconnect, with interconnects each being substantially longer than deep. The interconnects are disposed toward each other with a insulator region between them. A fusible conductor, spanning the insulator region, is attached at the top of the interconnects. The present device allows the length of the fusible conductor to be shortened, and results in a fuse link that can be consistently blown with a single laser pulse. Additionally, the fuse link can be used in a staggered layout. The staggered layout of parallel fuse links allows a high number of links in a relatively small area, with or without the use of tungsten barriers, and allows accessing all fuse links through a single fuse blow window.

Fusible links with improved interconnect structure

The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures. Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.

Array protection devices and method

A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip. Opposite rows of substantially flat cantilevered lead-fingers are attached by double-sided adhesive tape in thermal contact with the active face of a chip. The lead-fingers are routed in personalized paths over the face of the chip to cover a large surface area to aid heat dissipation. All wirebond connections between the lead-fingers and the chip are made at a centerline connection strip running down the center of the chip. Each of the cantilevered lead-fingers has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides increasing path length to prevent corrosive ingress over the chip face.

Personalized area leadframe coining or half etching for reduced

A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip. Opposite rows of substantially flat cantilevered lead-fingers are attached by double-sided adhesive tape in thermal contact with the active face of a chip. The lead-fingers are routed in personalized paths over the face of the chip to cover a large surface area to aid heat dissipation. All wirebond connections between the lead-fingers and the chip are made at a centerline connection strip running down the center of the chip. Each of the cantilevered lead-fingers has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face.

An insulator for covering an interconnection wiring level in a surface thereof on a semiconductor substrate containing semiconductor devices formed by curing a flowable oxide layer and annealing is provided. The annealing is carried out in the presence of hydrogen and aluminum to obtain a dielectric constant of the oxide layer to a value below 3.2. Also provided is electrical insulation between neighboring devices using the flowable oxide which is cured and annealed. In this case, the annealing can be carried out in hydrogen with or without the presence of aluminum.

Carbon-free hydrogen silsesquioxane with dielectric constant less than

Array protection devices and fabrication method

Array fuse damage protection devices and fabrication method

An improved insulation layer is formed by first preparing a solution by reacting water with an aminoalkoxysilane monomer in a solvent, using a critical mole ratio of water/monomer. After a sufficient aging period, the solution is coated onto a suitable surface, e.g. the surface of a semiconductor device, and then cured, in an essentially oxygen-free atmosphere, to a ladder-type silsesquioxane polymer. The insulation layer demonstrates excellent planarizing characteristics, while also exhibiting enhanced crack-resistance.

Planarizing ladder-type silsequioxane polymer insulation layer

A sequence of masking steps reduces the amount of transference of a workpiece among work stations and reduces certain tolerances required for mask alignment in the construction of integrated circuits, and a gray level mask suitable for photolithography. In the integrated circuit, masking layers are developed directly in a wafer for delineating vertical and horizontal portions of an electrically conductive path. The mask is constructed of a transparent glass substrate which supports plural levels of materials having different optical transmissivities. In the case of a mask employing only two of these levels, one level may be constructed of a glass made partially transmissive by substitution of silver ions in place of metal ions of alkali metal silicates employed in the construction of the glass. The second layer may be made opaque by construction of the layer of a metal such as chromium. Both the wafer and the mask are fabricated by a photoresist structure which is etched in specific regions by photolithographic masking to enable selective etching of exposed regions of the level of materials of differing optical transmissivities. Various etches are employed for selective etching of the photoresist and other ones of the layers. The etches include plasma etch with chloride ions to attack the chromium of the opaque layer, compounds of fluorine to attack the glass layer, and reactive ion etching with oxygen to attack the photoresist structure.

Growing community of inventors

Essex Junction, VT, United States of America

Ronald R Uttecht