International Business Machines Corporation

Ronald R Troutman

Peter Edwin Cottrell

Claude Louis Bertin

Richard Alan Haight

Jai P Bansal

William J Craig

Charles W Koburger, Iii

Supratik Guha

Wayne Frederick Ellis

Fuad Elias Doany

Robert L Wisnieff

Jerome Brett Lasky

Larry Alan Nesbit

Shinichi Kimura

Francis Roger White

Robert J Polastre

Henry J Geipel, Jr

William R Griffin

Yoshikazu Ichioka

Wayne I Kinney

Leslie C Jenkins

Richard R Garnache

John Michael Wursthorn

Joseph M Karasinski

Somanath Dash

Herbert C Cook

Disclosed is a pixel circuit consisting of MOS field-effect transistors (or of thin-film transistors), a capacitor, and an organic light-emitting diode that stores a voltage signal that is used to control the amount of light emitted from the pixel. This pixel circuit is used in a two-dimensional array to form an active-matrix OLED display. The amount of light emitted at each pixel during a frame time is controlled by dividing the frame time into many sub-frames and changing the stored voltage at the beginning of each sub-frame in such a way that the integrated time a voltage is stored during a frame time determines the total amount of light emitted.

Digitally driven gray scale operation of active matrix OLED displays

A thin film light used in displays is disclosed. The thin film light is an organic light generating thin film located between two electrodes. One electrode facing the display is transparent, while another electrode is a reflective patterned electrode. The patterned electrode is aligned with pixel displays. At least one polarizer is used to provide a light or dark display background. The thin film light may be a backlight for transmission displays. Alternatively, the thin film light may be a frontlight for reflective displays, where display illumination and imaging are performed over the same front side of the reflective display.

Thin film frontlighting and backlighting for spatial light modulators

Organic light emitting diodes having a transparent cathode structure is disclosed. The structure consists of a low work function metal in direct contact with the electron transport layer of the OLED covered by a layer of a wide bandgap semiconductor. Calcium is the preferred metal because of its relatively high optical transmissivity for a metal and because of its proven ability to form a good electron injecting contact to organic materials. ZnSe, ZnS or an alloy of these materials are the preferred semiconductors because of their good conductivity parallel to the direction of light emission, their ability to protect the underlying low work function metal and organic films and their transparency to the emitted light. Arrays of these diodes, appropriately wired, can be used to make a self-emissive display. When fabricated on a transparent substrate, such a display is at least partially transparent making it useful for heads-up display applications in airplanes and automobiles. Such a display can also be fabricated on an opaque substrate, such as silicon, in which previously fabricated devices and circuits can be used to drive the display.

Organic light emitting diodes having transparent cathode structures

In the formation of organic light emitting diodes with a transparent top electrode, it was discovered that many of the materials used for this electrode can readily diffuse at room temperature into the organic films, creating shorts and otherwise compromising the performance of the diode. A solution to this problem is disclosed which involves a method for the creation of a diffusion barrier which prevents diffusion of electrode materials into the substrate while enhancing the ability of the OLED to emit light through the top electrode.

Optically transparent diffusion barrier and top electrode in organic

An apparatus for testing for and classifying defects in a TFT/LCD array having gate lines and data lines. Devices are provided for activating cells of the array by applying gate pulses to the gate lines and pulses to the data lines. Devices are also provided for acquiring waveforms from data lines of the array. Additional devices sample the waveforms at selected points in time. A computer may be used to classify the waveforms to indicate whether defects are present and if present, the nature of the defects by comparing voltages of the waveform at the selected points in time.

Array tester for determining contact quality and line integrity in a

A charge pumping structure is disclosed for use in a substrate bias voltage generator. It includes a capacitor on a substrate region for coupling to a first node periodic voltage signals received at a second node. A first diode structure provides a current path from the first node to the substrate and a second diode structure provides a current path between the first node and a reference potential, which is typically the ground. The first diode structure includes a PN junction diode, an isolation ring for collecting minority charge carriers injected into the substrate and is constructed on a portion of the substrate that has a lower doping concentration than the underlying substrate portion establishing a built-in electric field which inhibits the flow of minority carriers from the first diode to the underlying substrate. The second diode structure may include a pocket type PN junction diode constructed so that majority carriers are prevented from moving back into the substrate from which the substrate bias voltage generator will have to remove them.

Charge pumping structure for a substrate bias generator

Disclosed is an overvoltage protection structure which when used with CMOS circuits it protects them from overvoltage conditions while minimizing latch-up conditions in the structure. It consists of a well region of an opposite conductivity to that of the substrate defining a pocket region having a conductivity type which is similar to that of the substrate. A first PN junction diode is formed in a portion of the well region and a second PN junction diode is formed in the pocket region. The two diodes have opposite polarity and they both are connected to a signal line in such a way that one of the two diodes will be forward biased if the voltage on the signal line exceeds the bounds of the power supply voltages. The pocket region is connected to a V.sub.SS terminal which is normally grounded and the well region is connected to a power supply V.sub.DD. The doping concentration in the well region is predetermined to have a gradient so that minority carriers injected from one of the diodes in the well region will be repulsed and prevented from moving into the substrate region where they would be majority carriers and they could cause latch-up in the structure or at the very least adversely affect the voltage level of the substrate. Instead the injected carriers recombine in the well region or are collected by the adjacent isolated pocket region. When the second diode is forward biased, the minority carriers are injected into the isolated pocket region and are prevented from reaching the substrate by the underlying well region. This prevents these carriers from affecting the operation of adjacent circuits.

Twin diode overvoltage protection structure

A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field-doping regions; and a dopant-transmitter during the ion-implantation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers self-aligned to the wells so that, with a subsequent masking step, oxide field isolations are defined over the doped oxide layers. A heat cycle is then used to drive the field dopants into the corresponding field-doping regions.

Process of making dual well CMOS semiconductor structure with aligned

A method is disclosed for fabricating series and/or parallel connected P channel and N channel FET device topologically connected in a CMOS configuration, where the individual FET devices share a common gate sandwiched between them, forming a five terminal device. A new device structure and complementary MOSFET circuitry is also disclosed. The disclosed process produces devices and circuits which overcome the main disadvantage of prior art CMOS transistors, namely excessive area consumption and parasitic effects.

Structure of stacked, complementary MOS field effect transistor circuits

A CMOS driver or pull up circuit is provided which includes a pull up transistor of a given conductivity type and a precharged bootstrap capacitor which discharges fully through a second transistor having a conductivity type opposite to that of the pull up transistor to the control gate or electrode of the pull up transistor. A third transistor may be used to initiate discharge by providing power supply voltage to the control gate of the pull up transistor.

CMOS bootstrapped pull up circuit

Process for fabrication of stacked, complementary MOS field effect

A simple process is provided which forms a bulk CMOS structure by depositing a layer of material which resists oxidation, e.g., a barrier layer of silicon nitride on an N- semiconductor substrate, forming a P well in the substrate through a given segment of the barrier layer, removing a first segment of the barrier layer to form N+ regions for N channel source and drain and N- substrate contact, removing a second segment of the barrier layer to form a P+ field region, removing a third segment of the barrier layer to form P+ regions for source and drain of a P channel device, forming a first control electrode having a given work function for the P channel device which acts as an ion barrier and then forming a second control electrode between the N channel source and drain regions having a work function different from that of the first control electrode.

Method of making high density complementary transistors

A memory system is provided wherein extended injection-limited programming techniques attain a substantially uniform programming behavior from an ensemble of fabricated devices or cells to provide the maximum obtainable voltage threshold shift within a minimum time period. In order to produce these desired results, a floating gate of a device is charged by applying to the control gate of the device a first voltage during a portion of this time period which produces an accelerating field in a dielectric layer disposed adjacent to the floating gate and then applying to the control gate during the remaining portion of this time period a second voltage of greater magnitude than that of the first voltage prior to or when the accumulation of charge on the floating gate causes a retarding field to be established in the dielectric layer.

Programming floating gate devices

A method is provided for making complementary field effect transistors in a semiconductor layer having a first portion including an N type transistor with a channel region defined by N+ source and drain regions and having a second portion including a P type transistor with a channel region defined by P+ source and drain regions. An insulating layer is disposed over the first and second portions with thin insulating films formed over the channel regions. The steps of the method include applying a masking layer over the insulating layer having an opening over one of the portions, introducing a first impurity into the channel region of the one portion for channel tailoring purposes, depositing a first conductive refractory material on the thin insulating film located over the channel region of the one portion, removing the masking layer, introducing a second impurity into the channel region of the other portion for channel tailoring purposes and depositing a second conductive material on the thin insulating film located over the channel region of the other portion and in contact with the first conductive material. The first and second conductive materials have different work functions. The first conductive material is, preferably, platinum silicide while the second conductive material may be aluminum.

Method of making dense complementary transistors

This teaches that by measuring the rate of change in gate current of an insulating gate field effect transistor, under normal operating conditions, the time required to achieve a predetermined change in source-to-drain current in the transistor can be found. Because changes in gate current depends more on sensitivity on charge trapping in the oxide than do changes in channel current, and since the gate current occurs only in the small region of electron emission, the effects on gate current are more quickly developed than the secondary effect of reduced channel current due to the charge in gate oxide caused by the presence of trapped electrons.

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Essex Junction, VT, United States of America

Ronald R Troutman