Inmos Limited

Ronald R Bourassa

Douglas Blaine Butler

Michael R Reeder

An improved process in making a polysilicon resistor suitable for use as a load resistor in a static memory wherein after the doping of the polysilicon, the device is annealed by exposing it to a rapid increase of ambient temperature (up to between 900 and 1200.degree. C.), maintaining the high ambient temperature for a controlled time (about 5 seconds) and then lowering the ambient tempertature at a rapid rate. This decreases resistances by one order of magnitude and significantly decreases the temperature activation energy of the resistor. This permits static memory cells to retain data even though the cell has high leakage currents, thereby improving final test yields.

Resistor with low thermal activation energy

An improved load resistor for a VLSI memory cell is formed in polysilicon by having P-type (such as boron) impurities in a middle region and n-type (such as phosphorous or arsenic) impurities on the sides, with the concentrations being in a range so that the thermal activation energy is below about 0.5 eV. Further, the middle region can be doped additionally with arsenic or phosphorous in an amount equal to or less than the boron. This gives good leakage current masking over a range of -55.degree. to +125.degree. C. without drawing excessive current, and is less sensitive to impurities.

Polysilicon resistor with low thermal activation energy

In making a polysilicon resistor in a polycide line, a thick oxide is established selectively to shield lightly doped polysilicon first from heavy doping and then from the silicide. Before adding silicide, a selected region of polysilicon broader than and including the site of the poly resistor is exposed, lightly doped, and then oxidized to establish a thick oxide, while other areas are protected by nitride. Then the nitride and any thin oxide on top of the polysilicon outside the broad area are removed, and the exposed polysilicon is heavily doped for low resistivity. The thick oxide shields the underlying lightly doped polysilicon from the heavy doping. Silicide is then added. Definition of the polysilicon resistor follows preferably using a two step process. When the silicide is etched, the thick oxide on top of the broad polysilicon area acts as an etch stop. Then the thick oxide and polysilicon resistor are etched.

Process for fabricating polysilicon resistor in polycide line

A poly layer on a substrate is covered with nitride. A reverse tone load implant mask and etch opens an area, which is then boron implanted. Controlled oxidation follows to grow oxide on the boron-doped region only, thereby thinning the poly there. Strip the nitride and then dope the poly layer. The oxide shields the boron-doped region from further substantial doping. Next, apply a poly definition photoresist mask. Etch the exposed oxide and poly to define a poly line having a boron-doped resistor therein. The difference in etch rates between heavily doped and lightly doped poly is compensated for by the adjustment of thickness of the boron-doped region. Hence, the etch for both types of poly concludes at about the same time, leaving the underlying layers substantially intact. Sources and drains may be implanted thereafter without an additional load implant mask.

Method for fabricating integrated circuits with polysilicon resistors

An improved process in making a polysilicon resistor suitable for use as a load resistor in a static memory wherein after the doping of the polysilicon, the device is annealed by exposing it to a rapid increase of ambient temperature (up to between 900.degree. and 1200.degree. C.), maintaining the high ambient temperature for a controlled time (about 5 seconds) and then lowering the ambient temperature at a rapid rate. This decreases resistance by one order of magnitude and significantly decreases the temperature activation energy of the resistor. This permits static memory cells to retain data even though the cell has high leakage currents, thereby improving final test yields.

Method of making polysilicon resistors with a low thermal activation

A process is described for anisotropically etching semiconductor products which include a lower dielectric layer, an intermediate polysilicon layer, and an upper silicide layer such as titanium silicide. A pattern-defining layer will normally overlie the silicide layer to define target areas to be etched. In a first step, the silicide is etched through using Freon 115 chloro, pentafluoroethane (C.sub.2 ClF.sub.5) in a plasma etching chamber conditioned to provide a reactive ion etch. The etch is completed in the same chamber using a second gas which includes an amount of Cl.sub.2 selected to etch anisotropically through the polysilicon layer without substantially etching the dielectric layer. Preferably, both etches occur after covering inner surfaces of the etching chamber with a material which releases molecules of the character included in the pattern-defining layer, such as Kapton, a polymide, in the disclosed example.

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Colorado Springs, CO, United States of America

Ronald R Bourassa