Mentor Graphics Corporation

Other

Ronald Press

Martin Keim

Etienne Racine

Wu-Tung Cheng

Jean-Francois Cote

Nilanjan Mukherjee

Yu Hu

Yu Jane Huang

Ruifeng Guo

Nagesh Tamarapalli

Liyang Lai

Jing Ye

Jay Babak Jahangiri

Aspects of the invention relate to test access architecture for stacked memory and logic dies. A test access interface for a logic die that is stacked under a memory die is disclosed. The disclosed test access interface can control testing logic core, interconnections with the memory die and with another logic die. The controlling of testing interconnections with the memory die is through a memory boundary scan register controller in the test access interface.

Test access architecture for stacked memory and logic dies

Aspects of the invention relate to test access architecture for stacked dies. The disclosed test access interface for a die can function as a stand-alone test access interface, allowing both pre-bond testing and post-bond testing of the die. In a stack of dies, the test access interface of a die may be enabled/disabled by the test access interface of an adjacent die.

Test access architecture for multi-die circuits

Test access architecture for stacked dies

Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed test patterns through one or more boundary scan cells. For instance, in one exemplary nonlimiting embodiment, a circuit is disclosed comprising one or more boundary scan cells coupled to primary input ports or primary output ports of a circuit-under-test. The circuit further includes a boundary scan cell controller configured to apply test control signals to the one or more boundary scan cells. In this embodiment, the controller is configured to operate in a mode of operation whereby the controller applies test control signals to the one or more boundary scan cells that correspond to test control signals used to control one or more internal scan chains of the circuit-under-test during testing. The control signals of this exemplary embodiment include an at-speed-clock signal generated outside of the boundary scan cell controller.

Reduced-pin-count-testing architectures for applying test patterns

A circuit to synchronously select one of the multiple clocks is presented. In one embodiment the selection circuit consists of four main blocks. These are the stable selects block, the decoder block, the synchronous selects block, and the output block. The stable selects block takes select signals as inputs and outputs a signal indicating whether the selects are stable or not, in addition to producing select signals that are synchronous to the current selected clock. The decoder block, decodes the select signals if they are stable, otherwise it re-circulates the previous values of the decoded clock select signals. The stable decoded select signals are then passed on to the synchronous selects block. This block outputs select signals in synchrony with their respective clocks. The synchronous select signals along with the stable decoded signals are used in the output block along with the clocks themselves to generate the final output clock. The transition from the first clock to the second clock is achieved with out any clips or glitches on the output clock. In order to eliminate the possibility of a glitch the first clock is disengaged from the output clock during the first clock's low state. This low state is maintained on the output clock until it is deemed safe to engage the second clock to the output clock during the second clock's low state.

Circuit for switching between multiple clocks

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West Linn, OR, United States of America

Ronald Press