International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Ronald Peter Luijten

Andreas Christian Doering

Mircea R Gusat

Casimer M DeCusatis

Claude Basso

Stefano Sergio Oggioni

Martin L Schmatz

Thomas J Brunschwiler

Kenneth Michael Valk

Fredy Daniel Neeser

Patricia Maria Sagmeister

Rolf Clauberg

Bruno Michel

Hillery C Hunter

Cyriel Johan Minkenberg

Juergen Koehl

Stephan Paredes

Francois Abel

Maria Gabrani

Norbert Schumacher

David J Webb

Gagandeep Singh

David L DeMaris

Hans Rudolf Schindler

Bernd Leppla

Beat Eugen Weiss

Mauro Spreafico

Phillip Stanley-Marbell

Nathalie Casati

Joerg-Eric Sagmeister

Joost VandeVondele

Abel Francois

A coarse-grained reconfigurable array accelerator for solving partial differential equations for problems on a regular grid is provided. The regular grid comprises grid cells which are representative for a physical natural environment wherein a list of physical values is associated with each grid cell. The accelerator comprises configurable processing elements in an accelerator-internal grid connected by an accelerator-internal interconnect system and memory arrays comprising memory cells. The memory arrays are connected to the accelerator-internal interconnect system. Selected ones of the memory arrays are positioned within the accelerator corresponding to positions of the grid cells in the physical natural environment. Thereby, each group of the memory cells is adapted for storing the list of physical values of the corresponding grid cell of the physical natural environment.

CGRA accelerator for weather/climate dynamics simulation

The present invention is notably directed to a printed circuit board, or PCB. This PCB has two main surfaces, each delimited by lateral edges, as well as lateral surfaces, each meeting each of the two main surfaces at one lateral edge. The present PCB further comprises a row of solder pads, which extends along a lateral edge of the PCB. Each solder pad is formed directly at the lateral edge and/or directly on a lateral surface (meeting one of the two main surfaces at said lateral edge). I.e., each pad interrupts a lateral edge and/or an adjoining lateral surface. One or more chips, e.g., memory chips, can be mounted on such a PCB to form an IC package. The above solder pad arrangement allows particularly dense arrangements of IC packages to be obtained. The present invention is further directed to related devices and methods of fabrication thereof.

Printed circuit board with edge soldering for high-density packages and assemblies

An electronic circuit card comprises a printed circuit board with electronic components. The electronic components comprise drivers for transmitting transmit (TX) signals and receivers for receiving receive (RX) signals, according to several groups of interface signals. There is further provided a connector edge, arranged at an edge of the card, and configured to allow the card to be connected to an external connector. This connector edge comprises two subsets of symmetric pins on respective (opposite) sides thereof. The drivers and the receivers are connected to the pins, for respectively conveying the TX signals and the RX signals. Pins are assigned such that, for each of the several groups of supported interface signals, any pin (of any of the subsets) connected to transmit TX signals is located opposite a pin (of the other subset) connected to receive RX signals. Pairs of consecutive pins (on each side) typically come in differential pairs.

Electronic circuit card with connector edge having alternated TX and RX pins assignment

A mechanism is provided for cooling electronic components of a printed circuit board module and for supplying power to the electronic components of the printed circuit board module. The computer module comprises a printed circuit board module, wherein the electronic components are attached to a first side of the printed circuit board module, and a cooling module being attached to a second side of the printed circuit board, being arranged in parallel to the printed circuit board and having a first layer being thermally and electrically conductive. The first layer is arranged such that heat is dissipated from the printed circuit board module and that power from a power source is supplied to the electronic components of the printed circuit board module.

Cooling electronic components and supplying power to the electronic components

Embodiments of the invention are directed to an integrated circuit (IC) package assembly, including: one or more printed circuit boards (PCBs); and a set of chip packages, each including: an overmold; and an IC chip, overmolded in the overmold, and wherein: the chip packages are stacked transversely to an average plane of each of the chip packages, thereby forming a stack wherein a main surface of one of the chip packages faces a main surface of another one of the chip packages; and each of the chip packages is laterally soldered to one or more of said one or more PCBs and arranged transversally to each of said one or more PCBs, whereby an average plane of each of said one or more PCBs extends transversely to the average plane of each of the chip packages of the stack. Further embodiments are directed to related devices and fabrication methods.

Dense assembly of laterally soldered, overmolded chip packages

A system to improve a Converged Enhanced Ethernet network may include a controller having a computer processor connected to a layer 2 endpoint buffer. The system may also include a manager executing on the controller to monitor the layer 2 endpoint buffer by determining buffer data packet occupancy and/or rate of change in the buffer data packet occupancy. The system may further include a reporter to notify a congestion source of the layer 2 endpoint buffer based upon the buffer data packet occupancy and/or rate of change in the buffer data packet occupancy.

Monitoring endpoint buffer occupancy to determine congestion in an ethernet network

Monitoring endpoint buffer occupancy to determine congestion in an Ethernet network

A method of constructing a mask for use in semiconductor device manufacturing is disclosed. A first shape that is related to mask construction is selected from a set of shapes. A second shape related to the mask construction is selected from the set of shapes. The first shape and the second shape are represented using a first shape vector and a second shape vector, respectively. A cluster is formed that includes the first shape and the second shape when the first shape vector and the second shape vector are within a selected criterion.

Automatic wafer data sample planning and review

A computer-implemented method for a computerized system having at least a first processor and a second processor, where each of the processors are operatively interconnected to a memory storing a set of data to be processed by a processor. The method includes monitoring data accessed by the first processor while executing, and if the second processor is at a shorter distance than the first processor from the monitored data, instructing to interrupt execution at the first processor and resume the execution at the second processor.

Computer program product for managing processing resources

A network device including at least one rate-limited-queue and multiple timer modules, the network device being operable to receive and/or transmit data flows from and/or to a communication network. Each data flow includes multiple data packets. The network device being further operable to limit the predetermined transmission rate of the respective data flow dependent on whether a data congestion in the communication network has been indicated, in such a way, that in case of an indicated congested communication network a respective timer module is associated to each of the data flows and/or each group of data flows, whereas the data packets of the respective data flows and/or group of data flows are buffered in the rate-limited-queue. Each data packet in the rate-limited-queue is transmitted with a limited transmission rate predetermined by the respectively associated timer module when the data packet is at the head of the rate-limited-queue.

Network device and method for operating network device

Apparatus and method of operating a crossbar switch () having a control logic, an output port scheduler (), n input ports (i, . . . , i) and m output ports (o, . . . , o), wherein information packets are routed from said n input ports to said m output ports, and wherein said output port scheduler () controls the sequence of packets output at said output ports (o, . . . , o). To ensure fairness regarding packet transfer/routing and the packet sequence, an input port number corresponding to the input port a new information packet is arriving at is stored in round-robin mode in a port number buffer (pnb). For output, said input port number is retrieved from said port number buffer (pnb) in round robin mode, too, and with this port number, address information regarding the packet is obtained from a control logic buffer of the crossbar switch ().

Method of operating a crossbar switch

Method and apparatus for providing a non-blocking routing network for establishing arbitrary connections between n primary nodes (m_n&#x2212;1) and N&#x2267;n secondary nodes (r_N&#x2212;1). The routing network requires less physical connections than a corresponding Clos routing network while having small transmission delays. One embodiment of the invention provides a routing network that is well suited for direct on-chip implementation due to the matrix structure of the routing network.

Method of providing a non-blocking routing network

Method and apparatus for ATM switching

Bit mapping apparatus and method

Growing community of inventors

Thalwil, Switzerland

Ronald Peter Luijten