International Business Machines Corporation

Corning Incorporated

Ronald Pete Luijten

Antonius Paulus Engbersen

Cyriel Johan Minkenberg

Francois Abel

Andreas Christian Doering

John Ulrich Knickerbocker

Martin L Schmatz

Alan Frederic Benner

Patricia Maria Sagmeister

Gottfried Andreas Goldrian

Mitch Gusat

Wolfgang Emil Denzel

Ferdinand Gramsamer

Mark Verhappen

Marco Heddes

Lawrence Jacobowitz

Florian Alexander Auernhammer

Subhash Laxman Shinde

Nikolaos Chrysos

Rolf Clauberg

Norbert Schumacher

Andreas Guenther Herkersdorf

Bernd Leppla

Ralph Heller

Stefano Sergio Oggioni

Thomas J Brunschwiler

Hillery C Hunter

Mircea R Gusat

Ilias Iliadis

Steven Paul Ostrander

Fredy Daniel Neeser

Juergen Koehl

Ken Van Vu

Jeannine Madelyn Trewhella

Michel Poret

Jeffrey Alan Kash

Peter L Buchmann

Richard Robert Grzybowski

David J Webb

William T Devine

Hamid Ahmadi

Johannes G Beha

Ton Engbersen

Ernst H Rothauser

Brewster Roe Hemenway, Jr

Phillip Stanley-Marbell

Cyriel J A Minkenberg

Jose Duato

Antonius J Engbersen

Erich Port

Charles Allen Murphy

Joerg-Eric Sagmeister

Andreas C Doering

Andreas Herkerdorf

DeCusatis M Casimer

Fran&ccedil;ois G Abel

Antonius Engberson

Laurent Nicolas

Rajaram Krishnamurthy

Francois G Abel

The present invention is notably directed to a printed circuit board, or PCB. This PCB has two main surfaces, each delimited by lateral edges, as well as lateral surfaces, each meeting each of the two main surfaces at one lateral edge. The present PCB further comprises a row of solder pads, which extends along a lateral edge of the PCB. Each solder pad is formed directly at the lateral edge and/or directly on a lateral surface (meeting one of the two main surfaces at said lateral edge). I.e., each pad interrupts a lateral edge and/or an adjoining lateral surface. One or more chips, e.g., memory chips, can be mounted on such a PCB to form an IC package. The above solder pad arrangement allows particularly dense arrangements of IC packages to be obtained. The present invention is further directed to related devices and methods of fabrication thereof.

Printed circuit board with edge soldering for high-density packages and assemblies

A printed circuit board (PCB) assembly includes a first PCB and a second PCB disposed substantially parallel and opposite to each other, such that a second side of the first PCB is opposite to a first side of the second PCB; wherein the second PCB has a first set of side connectors on its first side and a second set of side connectors on its second side, configured for both electrical power supply to and signal communication with the second PCB; the second PCB both electrically and mechanically connected to the second side of the first PCB via a first elastomeric connector; and the second PCB electrically connected to the first PCB via its second set of side connectors and a flexible electrical connector that is electrically connected to the second set of side connectors and the first PCB.

Method of forming a printed circuit board assembly

Assembly of printed circuit boards

A reliability system for a Converged Enhanced Ethernet network may include a plurality of end points each comprising a layer 4 transport layer, where each end point is connected to a data center bridging (DCB) layer 2 network. The system may also include an adaptor between the layer 4 transport layer and the DCB layer 2 network to translate at least one of flow and congestion control feedback signals, provided by at least one of the DCB network and the transport layer, to consolidated feedback signals for controlling transmission by the transport layer.

Lossless socket-based layer 4 transport (reliability) system for a converged ethernet network

A method for Remote Direct Memory Access (RDMA) of a memory of a processor. An address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address.

Address translation unit, device and method for remote direct memory access of a memory

An address translation unit for Remote Direct Memory Access (RDMA) of a memory of a processor is provided. The address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address.

A set of interlocking modules supports and connects a die containing lasers, a set of precision molded lenses and a set of beam switching elements. Another embodiment of the invention is a structure for mounting a logic chip and an optical chip on a chip carrier, with the optical chip being mounted on the side of the carrier facing the system board on which the carrier is mounted, so that radiation travels in a straight path from optical sources on the optical chip into optical transmission guides on the board.

Manufacturable optical connection assemblies

A switching device is able to route the arriving data packets according to data packet destination information to dedicated output ports. The switching arrangement has, for each set of input ports in the switching device, a set of output buffers with an output buffer for storing the payload of each data packet at an address in the output buffer which pertains to the same set of output buffers and belongs to the dedicated output ports. At least one of the output buffers has a set of output queues with an output queue for each output port for storing the address of each payload stored in the corresponding output buffer. An arbiter controls a readout order of the stored addresses. For the output buffers which pertain to the same set of output ports a multiplexer multiplexes according to the readout order the payloads from the output buffers to the output ports.

Switching arrangement and method with separated output buffers

A computer-implemented method for managing processing resources of a computerized system having at least a first processor and a second processor, each of the processors operatively interconnected to a memory storing a set of data to be processed by a processor, the method comprising: monitoring data accessed by the first processor while executing; and if the second processor is at a shorter distance than the first processor from the monitored data, instructing to interrupt execution at the first processor and resume the execution at the second processor.

Computer-implemented method of processing resource management

The present invention discloses a memory sharing mechanism based on priority elevation. In accordance with the present invention, there is provided an apparatus and method for transporting packets of data in a communication device, wherein each packet is assigned one of several priorities and received based on memory state information. The method comprises the steps of storing the received packets in a memory and modifying the assigned priority of any of the packets causing congestion within the memory.

Memory sharing mechanism based on priority elevation

A method and system for reducing arbitration latency employs speculative transmission (STX) without prior arbitration in combination with routing fabric scheduled arbitration. Packets are sent from source locations to a routing fabric through scheduled arbitration, and also through speculative arbitration, to non-contentiously allocate outputs that were not previously reserved in the routing fabric to the speculatively transmitted packets.

Method and system to reduce interconnect latency

Discloses a switching arrangement for packets of data, with several input ports and several output ports and which is determined for the transportation of incoming packets to one or more designated of the output ports and from there to a subsequent device. More particularly it relates to a switching arrangement and method wherein for each input port a set of output buffers is arranged, each set comprising an output buffer for each output port.

A method for automatically managing a virtual output queuing system in a switching fabric. The method includes detecting if a link is one of a non-operational-link and an operational-link. The link enables communication between a first-switching-unit and a second-switching-unit. If the link is the non-operational-link, the method further includes discarding at least one packet destined for the link. The discarding step further includes either dropping of the at least one packet or scheduling the at least one packet.

Method for automatically managing a virtual output queuing system

The present invention discloses a scalable flow-control mechanism. In accordance with the present invention, there is provided a switching device for transporting packets of data, the packets being received at the switching device based on flow-control information, the device comprising a memory for storing the packets, a credit counter coupled to the memory for counting a credit number of packets departing from the memory, and a scheduler unit coupled to the credit counter for deriving the flow-control information in response to the credit number. Moreover, a switching apparatus and a method for generating flow-control information is disclosed.

Scalable link-level flow-control for a switching device

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Horgen, Switzerland

Ronald Pete Luijten