Syphermedia International, Inc.

The Directv Group, Inc.

Rambus Inc.

Inside Secure

Other

Verimatrix, Inc.

Promtek Programmable Memory Technology, Inc.

Ronald Paul Cocchi

James Peter Baukus

Bryan Jason Wang

Lap Wai Chow

Gregory J Gagnon

Dennis R Flaharty

Christopher P Curren

Michael A Gorman

Raynold M Kahn

Jacob T Carson

Frances C McKee-Clabaugh

David Ha

Kevin T Collier

Matthew A Skubiszewski

Thomas H James

Peter M Klauss

Donald J Breier

Paul Ouyang

Raymond M Kahn

A camouflaged application specific integrated circuit is disclosed. The camouflaged ASIC includes at least one camouflaged FinFET, which includes a substrate of a first conductivity type, a fin, disposed on the substrate, the fin including a source region of a second conductivity type, a drain region of the second conductivity type, and a channel region of the first conductivity type. The camouflaged application specific integrated circuit also includes a gate disposed over and substantially perpendicular to the channel region, forming one or more transistor junctions with the fin. In one embodiment, the substrate includes a punch through stop (PTS) region of the second conductivity type disposed between the fin and the substrate, the PTS region electrically shorting the source region of the fin to the drain region of the fin.

Always-on FinFET with camouflaged punch stop implants for protecting integrated circuits from reverse engineering

A system and method for adding a source contact, a drain contact, and an apparent gate contact to a FinFET having a fin including a source region, a drain region, and a gate disposed over the fin forming one or more transistor junctions with the fin. The method comprises producing a source contact opening extending downward to a first region electrically coupled to the source region, a drain contact opening extending downward to a second region electrically coupled to the drain region, and a gate contact opening extending downward to a third region electrically isolated from the gate, and filling the source contact opening, the drain contact opening, and the gate contact opening with a conductive metal.

Electrically isolated gate contact in FINFET technology for camouflaging integrated circuits from reverse engineering

An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration.

Physically unclonable camouflage structure and methods for fabricating same

The camouflage technique described herein introduces programmed configuration inputs to Micro Netlists, creating Programmable Micro Netlists (PMNLs). PMNLs are a group of camouflaged and non-camouflaged cells that may be configured to perform one of several possible logic functions. They retain all the protective properties of non-programmable MNLs, but also allow for secure post-manufacture configuration of their aggregate logic function.

Secure logic locking and configuration with camouflaged programmable micro netlists

A camouflaged FinFET is disclosed. The camouflaged FinFET comprises a fin and a gate, disposed over and perpendicular to the fin. The fin includes a source region of a first conductivity type, a drain region of the first conductivity type, a channel region of a second conductivity type, the channel region disposed between the source region and the drain region, and a camouflaged fin region of the second conductivity type, the camouflaged Fin region at least partially rendering the camouflaged FinFET in an always-on condition and having a planar layout substantially indistinguishable from a fin region of an uncamouflaged FinFET.

Camouflaged FinFET and method for producing same

A method and an apparatus for camouflaging an application specific integrated circuit are disclosed. The ASIC comprises a circuit comprising a plurality of interconnected functional logic cells performing a logical function. In one embodiment, the method comprises accepting a coded description of the circuit, wherein the coded description describes the circuit in terms of components comprising a sequential logic component and a virtual camouflage component, generating a logical description of the circuit, the logical description of the circuit comprising a logical description of the virtual camouflage component, and replacing, in the logical description of the circuit, the logical description of the virtual camouflage component with a logical description of a functionally equivalent technology-dependent camouflaged component.

Method and apparatus for camouflaging an integrated circuit using virtual camouflage cells

A method and apparatus for brokering the enablement of the communication of encrypted media programs from a plurality of independent broadcasters to a plurality of receivers is disclosed. The system makes use of a pairing key for each provided service, which is differently encrypted by a pairing server and by the broadcaster providing the service. The encrypted versions of the pairing key are decrypted in a first receiver module using information known to the pairing service but not the broadcaster and in a second receiver module using information known to the broadcaster. The pairing key is used to cryptographically bind the first and second receiver modules.

Method and apparatus for supporting multiple broadcasters independently using a single conditional access system

A method and apparatus for controlling a group of the client devices to switch at least one client device of the group of client devices from a first conditional access system to a second conditional access system is disclosed. In one embodiment, the method comprises generating a group identifier identifying the group of the client devices, transmitting a first client device signaling message having the group identifier only to each client device of the identified group of client devices, the group identifier for storage in each client device of the identified group of client devices in non-volatile memory, and transmitting a second client device signaling message to plurality of client devices, the second client device message comprising the group identifier and signaling a switch of each of the identified group of client devices from the first conditional access system to the second conditional access system.

Signaling conditional access system switching and key derivation

A method, apparatus, article of manufacture, and a memory structure for providing a security infrastructure that permits the programming of limited hardware resources that can accept newly downloaded applications and securely support a very large number of services offered by content providers each have the potential to utilize their own independent CAS/DRM system. The CE device owner can consume content from a variety of sources and enable switching among different and existing CAS/DRM security profiles as required by the content provider applications loaded in CE devices.

Method and apparatus for a blackbox programming system permitting downloadable applications and multiple security profiles providing hardware separation of services in hardware constrained devices

A method, apparatus, article of manufacture, and a memory structure for inserting a watermark in a media program is described. In an exemplary embodiment, the method comprises the steps of receiving data comprising the media program in the receiver disposed at a subscriber station, generating a watermark, the watermark generated at least in part according to a secure data processor-unique identifier irreversibly stored in the secure data processor, processing the received data to reproduce the media program, and inserting portions of the generated watermark in the reproduced media program at locations determined at least in part according to the secure data processor-unique identifier to produce a watermarked media program provided for display.

Method and apparatus for hardware-enforced, always-on insertion of a watermark in a video processing path

A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. Additionally, post processing may be performed on GDS layers to provide a realistic fill of the empty space so as to resemble structural elements found in a functional circuit.

Method and apparatus for camouflaging a standard cell based integrated circuit with micro circuits and post processing

A method, apparatus, article of manufacture, and a memory structure for securely providing data for use by a hardware device of a receiver. The method utilizes a product provisioning key (PPV) held secure from other entities that can be unlocked and used with a secret value securely and unchangeably stored in the hardware device.

Growing community of inventors

Seal Beach, CA, United States of America

Ronald Paul Cocchi