Adeia Semiconductor Bonding Technologies Inc.

Other

Sgs-thomson Microelectronics Limited

Ronald Patrick Green

Stuart E Wilson

Belgacem Haba

Ilyas Mohammed

Wael Zohni

Masud Beroz

Yoichi Kubota

Jesse B Thompson

Richard Dewitt Crisp

Giles Humpston

James Gill Shook

David W Wallis

Andy Stavros

Nicholas J Colella

Sridhar Krishnan

Ming Tsai

David M Osika

Jerome C Howell

System and method of applying pulsed electromagnetic fields (PEMF) to a human user's body. Here an electrically isolated antenna is applied to a portion of the body. This antenna is connected to a PEMF power source comprising a modified Blumlein dual transmission line transformer circuit with emphasis on miniaturization. Each transmission line comprises a substantially planar PC board mounted conducting strip configured in a meander pattern, and separated from at least one split ground plane by at least one substantially planar dielectric material and at least one split ground plane. This in turn is powered by a low voltage power supply, resonant transformer. The Blumlein circuit is charged and discharged by a processor controlled high-speed switch according to user selected time settings, and can produce outputs substantially above 1 kV. Relative to prior art devices, the system enables much smaller, lighter, and less costly PEMF implementations.

Pulsed electromagnetic field therapy system and method

A transmission structure having high propagation velocity and a low effective dielectric loss. The structure comprises a dielectric, a first reference conductor disposed below the dielectric, a signal conductor disposed above the dielectric, and a second reference conductor disposed over the signal conductor. The second reference conductor has a recess portion facing the signal conductor, the recess portion defining a gap between the second reference conductor and the signal conductor. The gap may be filled with air which has a relative dielectric constant approximately equal to one (1). Because of the physical and dielectric constant characteristics of the gap, the structure concentrates an electric field in the gap resulting in an effective dielectric constant approximately (approaching) one (1) and an effective dielectric loss approximately equal to zero (0). Thus, the structure exhibits a propagation velocity approximately equal to the speed of light.

Low loss RF transmission lines having a reference conductor with a recess portion opposite a signal conductor

A cavity resonator is provided which includes a shielded enclosure enclosing a volume and a unitary conductor disposed within the volume, the unitary conductor having a first inductor portion and a transmission line portion. The transmission line portion is included in a transmission line having a reference conductor separated from the transmission line portion by a dielectric element. An active semiconductor device is coupled to the unitary conductor, and is operable to conduct a current to the unitary conductor at a resonant frequency of the unitary conductor.

High Q cavity resonators for microelectronics

A microelectronic assembly includes a microelectronic package having a microelectronic element with faces and contacts, a flexible substrate spaced from and overlying a first face of the microelectronic element, and a plurality of conductive posts extending from the flexible substrate and projecting away from the first face of the microelectronic element, at least some of the conductive posts being electrically interconnected with the microelectronic element. The package includes a plurality of support elements disposed between the microelectronic element and the substrate and supporting the flexible substrate over the microelectronic element. At least some of the conductive posts are offset from the support elements. The assembly includes a circuitized substrate having conductive pads confronting the conductive posts of the microelectronic package, whereby the conductive posts are electrically interconnected with the conductive pads.

Microelectronic packages and methods therefor

A stacked microelectronic assembly includes a base substrate having conductive elements projecting from a bottom surface thereof and a first microelectronic subassembly underlying a bottom surface of the base substrate. The first microelectronic subassembly includes a first dielectric substrate, a first microelectronic element connected with the first dielectric substrate and first conductive posts projecting from the first dielectric substrate toward the bottom surface of the base substrate for electrically interconnecting the first microelectronic element and the base substrate. The assembly also has a second microelectronic subassembly overlying the base substrate. The second microelectronic subassembly includes a second dielectric substrate, a second microelectronic element connected with the second dielectric substrate and second conductive posts projecting toward the top surface of the base substrate for electrically interconnecting the second microelectronic element and the base substrate. The first microelectronic subassembly has a first height and the conductive elements projecting from the bottom surface of the base substrate have a second height that is greater than the first height of the first microelectronic subassembly.

Stack microelectronic assemblies

An assembly is provided which includes a first circuit panel having a top surface, a first dielectric element and first conductive traces disposed on the first dielectric element. In addition, a second circuit panel has a bottom surface, a second dielectric element and second conductive traces disposed on the second dielectric element, where at least a portion of the second circuit panel overlies at least a portion of the first circuit panel. The assembly further includes an interconnect circuit panel having a third dielectric element which has a front surface, a rear surface opposite the front surface, a top end extending between the front and rear surfaces, a bottom end extending between the front and rear surfaces, and a plurality of interconnect traces disposed on the dielectric element. The bottom end of the interconnect element abuts the top surface of the first circuit panel and the top end abuts the bottom surface of the second circuit panel, where at least some of the first conductive traces are in conductive communication with the second conductive traces through the interconnect traces.

Assembly including vertical and horizontal joined circuit panels

A packaged chip is provided which includes a package element on which a signal-bearing conductive trace has an edge laterally adjacent to an edge of a reference conductive trace (e.g., ground trace) on the same face of a dielectric element, the two traces together functioning as a capacitor. In a particular embodiment, the laterally adjacent traces provide shunt capacitance to compensate for an inductance in a signal path to the chip which includes the signal-bearing conductive trace. In a variation thereof, a transmission line or waveguide is provided which includes the signal-bearing conductive trace and reference trace. In further variations, transmission lines are provided which include one or more metal layers of a package element, separated from each other by a thickness of a dielectric element included in the package element or the air gap between the package and a circuit panel.

Packaged chip having features for improved signal transmission on the package

A microelectronic package includes a microelectronic element having faces and contacts and a flexible substrate spaced from and overlying a first face of the microelectronic element. The package also includes a plurality of conductive posts extending from the flexible substrate and projecting away from the first face of the microelectronic element, wherein at least some of the conductive posts are electrically interconnected with the microelectronic element, and a plurality of support elements supporting the flexible substrate over the microelectronic element. The conductive posts are offset from the support elements to facilitate flexure of the substrate and movement of the posts relative to the microelectronic element.

A method for monitoring the pH of a patient includes the step of providing a magnetic resonance system having a magnet with a bore configured to receive a portion of a finger of a patient without receiving a substantially larger portion of the body of the patient. The method proceeds by inserting the finger of the patient into the bore of the magnet and monitoring the pH level of capillary bed tissue in the finger with the magnetic resonance system. Preferably, the system is configured to monitor the spectrum of phosphorus-31 metabolites in the finger and produce information in the form of a normalized phosphorous integral ratio indicative of the spectral area in order to alert an operator of the occurrence of a condition in which the normalized phosphorous integral ratio is greater than one in the setting of decreasing pH, as indicative of capillary bed tissue shock--lactic acidosis. In line with the above, a digital magnetic resonance system includes a superconducting magnet for producing a magnetic field for magnetic resonance monitoring purposes, and a control system operatively coupled to the magnet for cooperating with the magnet in order to produce and display magnetic resonance information related to the portion of the body of a patient. The magnetic has a bore for receiving a portion of the body of a patient, and the bore has a size sufficient to receive a portion of a linger of a patient without receiving a substantially larger portion of the body of the patient. Preferably, the magnet is sufficiently small to enable use in a conventional hospital operating room.

Digital magnetic resonance shock-monitoring method

The present invention is directed to a voltage controlled single-package integrated circuit device, capable of thermal compensation, for biasing a quasi-linear bipolar device. The bias circuit also provides a low impedance source to a RF device so that the bias point does not dynamically change with the RF signal, thus improving linearity. Changes in the base-emitter voltage level of the RF device are monitored by a reference diode to provide automatic temperature compensation. The reference diode is in close thermal proximity to the RF device, allowing for accurate thermal tracking. The base-emitter voltage may be electronically adjusted by means of a control voltage input, such being suitable for hook-up to a computer system having a digital to analog convertor thereby allowing for fine voltage adjustments. The control voltage may also be used to adjust the class of operation of the RF device or provide external temperature control.

Voltage controlled integrated circuit for biasing an RF device

Linear high gain (greater than 20 dB) and high power (greater than +20 dbm) devices for RF power amplifiers are achieved using either fully monolithic or hybridized versions of silicon MMIC two-stage cascaded amplifiers. The device features three feedback loops in conjunction with a DC biasing network. Resistor-capacitor feedback circuits utilize only two capacitive elements which are provided as a single three-terminal element having a common lower plate.

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San Jose, CA, United States of America

Ronald Patrick Green