Northrop Grumman Systems Corporation

Trw Limited

Ronald P Smith

Mark Kintis

Harvey L Berger

William Marvin Skones

Andrew Donovan Smith

Donald R Martin

Vincent C Moretti

Craig R Talbott

Bert K Oyama

Shimen K Claxton

Eric R Wiswell

Daniel R Lane

Konstantinos Makrygiannis

Mark K Christopher

Allen F Conrad

Eric L Upton

Barry Ross Allen

Oliver W Saunders

David Joseph Brunone

Kenneth E Westall

Hanna S-h Hsu

Anthony D Patire

Maneesh Goyal

Andy Chan

Jeffrey B Warner

A phased-array antenna system includes antenna elements of an RF front-end that each propagate a wireless beam portion. A digital beamforming system generates a digital beam corresponding to the wireless beam that is transmitted or received from the phased-array antenna system. Digital beamforming processors are each associated with a proper subset of the antenna elements. The digital beamforming processors can be collectively configured to iteratively process digital beam portions of the digital beam in a plurality of iteration levels comprising a lowest iteration level associated with lowest-level digital beam portions corresponding to the respective wireless beam portions at each of the respective antenna elements and a highest iteration level associated with the digital beam. Each digital beam portion associated with a given iteration level includes a sum of lesser digital beam portions from a next lower iteration level.

Phased-array antenna system

Systems and methods for combining digital input signals in an oversampled synthesizer system are provided. An inverse Fourier transform component is configured to receive a plurality of digital input signals, having a first sampled rate, and produce a corresponding representation of a wideband signal as a plurality of parallel outputs. A plurality of digital filters are each configured to apply a transfer function to an associated one of the parallel outputs to produce a filtered output. A number of filters in the plurality of digital filters is less than a number of parallel outputs of the inverse Fourier transform component, such that at least one of the parallel outputs is not provided to any filter of the plurality of digital filters. An interpolation component combines the plurality of filtered outputs into a wideband digital output signal having a second sampled rate.

Oversampled synthesizer systems and methods

A fast Fourier transform (FFT) circuit from which unneeded butterfly computation modules can be effectively pruned for specific applications. Each module that is not needed is pruned by injecting zero signals into it, thereby minimizing the power dissipated in the pruned circuit. A multiplexer integrated into each butterfly module output (or input) line allows the line signal to be either forced to zero or allowed to carry a nonzero signal.

Power saving zero pruning algorithm for fast fourier transform (FFT) circuitry

A communications system includes an antenna that produces a series of beams which divide a service region into a plurality of contiguous cells, and dynamically modifies cell boundaries so that the system's allocated communication spectrum is efficiently utilized.

Dynamic beam width selection for non-uniform density multiple access cells

A discrete Fourier transform (DFT) filter bank with stack shift capability, configured, for example, as an analyzer, but equally applicable to a synthesizer, and implemented as a polyphase filter. The DFT filter bank includes a complex modulator for multiplying the input signals x(m), x(m) . . . x(m) by a complex modulator e(m). In order to keep the coefficients for the polyphase filter real, the coefficients are modulated by a DFT twiddle factor e. The use of the DFT twiddle factor enables the hardware to be reduced significantly. For example, for an 8 phasetap filter, only 8 selectable negators are required as opposed tofor known DFT filter banks.

Polyphase filter with stack shift capability

Methods and devices for demodulators for continuous phase modulation waveforms. A modulated sampled signal is received. A consecutive sequence of the modulated sampled signal is buffered. The consecutive sequence is compared with all possible valid modulated sampled signals. A bit decision representing a demodulation of the consecutive sequence of the modulated sampled signal is determined based on a closest valid modulated sampled signal located closest to the consecutive sequence of the modulated sample signal in a constellation.

Discritized phase constellation continuous phase modulation demodulator

A receiver ( ) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver ( ) includes a specialized LNA ( ), frequency down-converter ( ) and ADC ( ) to perform the wideband signal processing while maintaining receiver performance. The frequency down-converter ( ) employs a suitable mixer ( ), BPA ( ), attenuator ( ), and transformer ( ) that are tuned to provide the desired frequency down-conversion and amplitude control over the desired wideband. The down-converter devices are selected depending on the particular performance criteria of the ADC ( ). A specialized digital channelizer ( ) is included in the receiver ( ) that receives the digital signal from the ADC ( ), and separates the signals into the multiple channels. In one embodiment, the frequency down-conversion is performed in a single down-conversion process, and the ADC ( ) employs delta-sigma processing to provide digital conversion over the complete frequency band. In an alternate embodiment, the frequency down-conversion is performed in a double down-conversion process so that a less complex ADC ( ) can be used.

Wireless telecommunications multi-carrier receiver architecture

A receiver ( ) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver ( ) includes a specialized LNA ( ), frequency down-converter ( ) and ADC ( ) to perform the wideband signal processing while maintaining receiver performance. A specialized digital channelizer ( ) is included in the receiver ( ) that receives the digital signal from the ADC ( ), and separates the signals into the multiple channels. In one embodiment, the frequency down-conversion is performed in a single down-conversion process, and the ADC ( ) employs delta-sigma processing to provide digital conversion over the complete frequency band.

Multi-carrier receiver including an analog-to-digital converter for a wireless telecommunication system

Architecture for multi-carrier receiver

A channelizer ( ) for a multi-carrier receiver including a plurality of digital sub-band tuners (DSBTs) ( ). Each DSBT ( ) digitally filters individual carrier data bits from a digital multi-carrier data stream based on a programmable center frequency. Each DSBT ( ) further digitally filters the individual carrier data stream based on a programmable bandwidth. The DSBTs ( ) can be allocated based on modulation format, center frequency, or both. The channelizer ( ) is therefore able to process narrowband carrier data streams as well as wideband carrier data streams. One embodiment of the channelizer ( ) has a plurality of sub-channelizers ( ) and a switch matrix ( ). The sub-channelizers ( ) filter individual carrier data streams from a multi-carrier data stream. The switch matrix ( ) is coupled to the sub-channelizers ( ) and routes the individual data streams to the sub-channelizers ( ) in a desired configuration.

Channelizer for a multi-carrier receiver

A method of packet concatenation in TDMA transmission is provided. The method includes the step of transmitting from a terminal in a first time slot ( ), including overhead information ( ) and symbols representing terminal data ( ). The method also includes the step of transmitting from a terminal (possibly the same terminal) in a subsequent time slot ( ), including a subset of the overhead information ( ) and symbols representing terminal data ( ). The subsequent time slot may be a consecutive time slot. The overhead information may include, for example, guard time ( ), ramp time beam settling time ( ) and a preamble ( ).

Packet concatenation for increased transmission capacity

A wireless communication system operates a power amplifier ( ) in an earth terminal ( ) in a non-saturated mode of operation to transmit communication signals over a communication uplink to a communication satellite ( ). The satellite operates a power amplifier ( ) in a saturated mode of operation to transmit communication signals over a communication downlink to terminal ( ). Operating the amplifiers in the different modes of operation increases efficiency.

Asymmetric bandwidth wireless communication techniques

The present invention provides a method and apparatus (,) for iteratively decoding data which has been encoded with contatenated codes. The apparatus (,) includes pipelined and cascaded decoder processors (,and,) connected to a multiple block memory device (,), through a multiplexing and data control block (,). A data decision element (,) is provided for generating decoded output data. The method includes receiving encoded data (,) while data already received is processed iteratively by decoder processors in a pipelined fashion. Decoder processors are designated to perform particular iterations (,) of an iterative decoding process which are performed simultaneously. As a decoder processor completes processing its designated iteration on a block of data, the decoder processor outputs decoding information (,) to the decoding processor designated to perform the subsequent iteration. Upon completion of all iterations for a block of data, the method includes generating output (,) consisting of the decoded data block. The method provides that once processing is complete on a data block, the memory block is made available (,) for the storing of new encoded input data.

Pipelined architecture to decode parallel and serial concatenated codes

An adaptive transceiver architecture which reallocates communications resources in real time based on the amount of bandwidth being used in communications channels in the system. The transceiver receives communications signals from a plurality of communications beam spots. Each communications beam spot has a predefined bandwidth divided into non-overlapping subbands. The transceiver further comprises a plurality of front end signal conditioners for receiving communications signals from an equal plurality of communications beam spots. A predetermined number of the conditioned signals are then combined by an interconnect. The interconnect receives composite signals from the front end signal conditioners, and it combines at least first and second communications signals from first and second respective composite signals to form an output processing signal. The first and second communications signals are received by the receiver from first and second communications beam spots, respectively, and the first and second composite signals are output from the first and second corresponding front end signal conditioners.

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Redondo Beach, CA, United States of America

Ronald P Smith