National Semiconductor Corporation

Ronald P Kovacs

Euisik Yoon

Robert W Allison, Jr

Albert M Bergemont

Michael E Thomas

Ali A Iranmanesh

Rick C Jerome

George E Ganschow

Frank Marazita

Brian McFarlane

Lawrence K Lam

James L Bouknight

A dielectric structure on a substrate includes a primary dielectric layer on the substrate, the primary dielectric being a metal oxide, such as tantalum pentoxide, having a high dielectric constant, and a secondary dielectric layer, such as an oxide or nitride of silicon, on the primary dielectric layer. In one embodiment, a multi-layer structure includes a second primary dielectric layer disposed on the secondary dielectric layer, and a second secondary dielectric layer disposed on the second primary dielectric layer, each primary dielectric layer being in a first crystalline state characterized by low leakage current for a given applied electrical field. A method of forming a dielectric structure on a substrate includes forming a layer of a primary dielectric, which is a metal oxide having a high dielectric constant, forming a secondary dielectric layer on the primary dielectric layer, and annealing the primary dielectric layer.

Method of providing a dielectric structure for semiconductor devices

A vertical fuse structure including a lightly-doped shallow emitter 30 provides improved fusing characteristics. The structure includes a buried collector 14, an overlying base 30, and an emitter 44 above the base 30. In one preferred embodiment, the emitter 44 extends about 0.2 microns from the upper surface and has a dopant concentration of about 8.times.1019 atoms of arsenic per cubic centimeter at the surface. A lightly doped base region 30 extends for about 0.46 microns below the emitter 44 to the collector 14. The upper surface of emitter 44 includes a metal contact 60. Heating the metal 60/emitter 44 interface to its eutectic melting point using a current or voltage pulse causes the aluminum to short through the emitter 44 to the base 30. Shorting the emitter programs the fuse. A second preferred embodiment uses polysilicon as an interconnecting medium. Mass transport of aluminum atoms through the polysilicon allows aluminum to collect at an interface between the polysilicon and an underlying single crystal silicon layer. Aluminum atoms are supplied from a contact metal. A barrier metal between the contact metal and an underlying polysilicon contact to the emitter is not present. Inhibiting or replacing a TiSi.sub.2 layer over the fuse emitter contact provides better reproducible fusing action. PtSi replaces TiSi.sub.2 if formed over the fuse emitter contact. Separate fuse base implants for the vertical fuse change BJT parameters for improved fusing characteristics. In still another preferred embodiment, codiffusing N type and P type dopants from the polysilicon emitter contact drops a separate fuse mask. The P type codiffused dopants diffuse ahead of the N type emitter dopants into the single crystal to change the base parameters to provide a decreased gain.

Vertical fuse device

A method of and apparatus for processing semiconductor wafers which include observing optical characteristics of exposed undeveloped photoresist, without removing the wafers from the stepper is disclosed. The present invention includes the steps of loading a wafer having a layer of photoresist into a photolithography system, exposing the photoresist in accordance with an initial set of control parameters including exposure time, position of the wafer within the photolithography system, and/or focus change. Prior to developing the photoresist, optical characteristics of the exposed photoresist are observed using a phase contrast microscope which detects latent images. Then, according to the observations of the latent image, the initial set of control parameters are adjusted to generate a second set of control parameters.

Photolithography control system and method using latent image

A process flow for fabricating a self-aligned stacked gate EPROM cell that uses a CVD tantalum oxide film to replace ONO as a control gate dielectric. Tungsten replaces polysilicon as the control gate. Both the dielectric deposition and cell definition steps of the process flow are performed in a back-end module to improve dielectric integrity in the memory cells by minimizing high temperature exposure of the tantalum oxide film.

Self-aligned stacked gate EPROM cell using tantalum oxide control gate

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Mountain View, CA, United States of America

Ronald P Kovacs