International Business Machines Corporation

Apple Inc.

Other

Ronald P Hall

Christopher Michael Abernathy

Jonathan James DeMent

Michael Lance Karm

David James Shippy

Albert James Van Norstrand, Jr

Ian D Kountanis

David Mui

Giles R Frazier

Kurt Alan Feiste

Brian Robert Mestan

Robert Alan Philhower

Mahesh K Reddy

Balaram Sinharoy

Mary Douglass Brown

Conrado Blasco

Todd Alan Venton

Shyam Sundar

Balaji Kadambi

Hung Qui Le

Richard Louis Arndt

Raul Esteban Silvera

Ramesh B Gunna

Timothy Hume Heil

David James Williamson

David Edward Kroesche

Muawya M Al-Otoom

Jeffrey Powers Bradford

Niket K Choudhary

Jonathan Y Tong

Ilhyun Kim

Edwina Conley

André Seznec

Jerome Raynor

Lydia Mai Do

Thuong Quang Truong

Alexander Erik Mericas

Peichun Peter Liu

Venkat Rajeev Indukuru

Gavin Balfour Meil

James Nolan Hardage

Richard William Doing

Rohit Kumar Gupta

Brett Stanley Feero

Richard F Russo

Alvan Wing Ng

Kevin Neal Magill

Conrado Blasco-Allue

Pruthivi Vuyyuru

Douglas C Holman

Deepak Limaye

Zhong Liang Wang

Christopher Colletti

Brian Patrick Hanley

Ethan R Schuchman

Michael D Snyder

Kevin C Stelzer

Anthony Willis

Abhishek Kumar

James O Tingen

Toni Hall

Siavash Zangeneh Kamali

Giles Roger Frazier

A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.

Prediction confirmation for cache subsystem

An apparatus includes an instruction cache circuit and an instruction fetch circuit. The instruction fetch circuit is configured to retrieve, from the instruction cache circuit, a fetch group that includes a plurality of instructions for execution by a processing circuit, and to make a determination that the fetch group includes a control transfer instruction that is predicted to be taken. A target address associated with the control transfer instruction is directed to an instruction within the fetch group. The instruction fetch circuit is further configured to, based on the determination, alter instructions within the fetch group in a manner that is based on a type of the control transfer instruction.

Using a next fetch predictor circuit with short branches and return fetch groups

Disclosed techniques relate to trace caches. Trace cache circuitry may identify traces that satisfy one or more criteria. Generally, internal branches of a trace should satisfy a threshold bias level in a particular direction. To achieve this goal, the processor may initially assume that branches meet the threshold, track their usefulness in the trace context over time, and prevent inclusion of branches that fall below a usefulness threshold (which indicates that those branches are not sufficiently biased). Branches that do not meet the threshold may be added to a Bloom filter, for example. Usefulness may be tracked during trace training, when valid in a trace cache, or both.

Trace cache with filter for internal control transfer inclusion

An embodiment of an apparatus includes a processing circuit and a system memory. The processing circuit may store a pending request in a buffer, the pending request corresponding to a transaction that includes a write request to the system memory. The processing circuit may also allocate an entry in a write table corresponding the transaction. After sending the transaction to the system memory to be processed, the pending request in the buffer may be removed in response to the allocation of the write entry.

Virtual channel support using write table

A modular tire lifting assembly includes a yoke that has a pair of arms which are spaced apart from each other such that t a vehicle tire can be positioned between the pair of arms. The yoke is comprised of a plurality of modular sections such that the yoke can be disassembled for storage in a vehicle. A first handle and a second handle are provided and either can be removably attachable to the yoke. Either the first handle or the second handle angles upwardly from the yoke when removably attached to the yoke thereby facilitating the yoke to lift the vehicle tire when either the first handle or the second handle is urged downwardly. Additionally, the second handle has a length that is less than a length of the first handle.

Modular tire lifting assembly

A system and method for efficiently handling maintenance requests among multiple processors. In various embodiments, a given processor of multiple processors receives a maintenance request. If maintenance requests are not currently being blocked, then the given processor determines a type of the maintenance request and updates one or more maintenance type counters based on the type. If one or more counters exceed a threshold, an indication is generated specifying maintenance requests received at a later time are to be held. The received maintenance request is processed. Different types of maintenance requests are used for invalidating entries in the instruction cache, for invalidating entries in a TLB and for synchronizing page table updates. Afterward, software applications continue processing. Forward progress of the software applications is measured using one or more metrics. If forward progress has been achieved, then one or more maintenance type counters are reset.

Method to ensure forward progress of a processor in the presence of persistent external cache/TLB maintenance requests

A processor includes a mechanism for disabling a memory array of a branch prediction unit. The processor may include a next fetch prediction unit that may include a number of entries. Each entry may correspond to a next instruction fetch group and may store an indication of whether or not the corresponding the next fetch group includes a conditional branch instruction. In response to an indication that the next fetch group does not include a conditional branch instruction, the fetch prediction unit may be configured to disable, in a next instruction execution cycle, the memory array of the branch prediction unit.

Fetch predition circuit for reducing power consumption in a processor

Various embodiments of a method and apparatus for flushing a cache are disclosed. In a system, a cache memory is accessible by an execution circuit. The execution circuit executes instructions and may utilize data and/or instructions stored in the cache. A flush circuit is also coupled to the cache. Responsive to execution of a power down instruction by the execution circuit, the flush circuit performs a cache flush. If a control state is asserted in a control register, the flush circuit generates a dummy event upon completing the cache flush. Responsive to generating the dummy event, a processor core that includes the execution circuit is inhibited from being powered down.

Cache flush method and apparatus

A system that includes circuitry to access memories in both coherent and non-coherent domains is disclosed. The circuitry may receive a command to access a memory included in the coherent domain and generate one or more commands to access a memory in the non-coherent domain dependent upon the received command. The circuitry may send the generated one or more commands to the memory in the non-coherent domain via communication bus.

Accessing memories in coherent and non-coherent domains in a computing system

Reducing power consumption in a processor

A system and method for efficiently indicating branch target addresses. A semiconductor chip predecodes instructions of a computer program prior to installing the instructions in an instruction cache. In response to determining a particular instruction is a control flow instruction with a displacement relative to a program counter address (PC), the chip replaces a portion of the PC relative displacement in the particular instruction with a subset of a target address. The subset of the target address is an untranslated physical subset of the full target address. When the recoded particular instruction is fetched and decoded, the remaining portion of the PC relative displacement is added to a virtual portion of the PC used to fetch the particular instruction. The result is concatenated with the portion of the target address embedded in the fetched particular instruction to form a full target address.

Immediate branch recode that handles aliasing

A winch mounting kit includes a first mount that may be removably coupled to a stanchion. The first mount may have a winch is removably attached thereto such that the winch is secured on the stanchion. A second mount is provided that may be removably coupled to a horizontal support. The second mount may have the winch being removably attached thereto such that the winch is secured on the horizontal support. A third mount is provided that may be removably coupled to a vertical support. The third mount may have the winch being removably attached thereto such that the winch is secured to the vertical support.

Winch mounting kit

A method, system, and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycles of the single branch, backwards short loop, rather than from the instruction cache.

Retrieving instructions of a single branch, backwards short loop from a local loop buffer or virtual loop buffer

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Cedar Park, TX, United States of America

Ronald P Hall