International Business Machines Corporation

Ronald N Schulz

Seiki Ogura

Mark E Jost

Louis L Hsu

David Louis Harame

Gary Bela Bronner

Nivo Rovedo

Jacob Riseman

Adam D Ticknor

Taqi Nasser Buti

James E Currie

Fang-shi J Lai

Bill guard for a cap

A wafer polishing fixture is disclosed containing a first liquid film confined by a non-porous but flexible enclosure for distributing evenly the applied polishing forces across the surface of a wafer supported by the confined liquid. The fixture comprises a flexible, non-porous template with a pocket for receiving a wafer to be polished. A washer is placed between a carrier and the template pocket. A film of water fills the bottom of the pocket and is confined with the aid of the washer and by an overlying porous pad extending across the pocket and having a non-porous sheath facing the liquid. A second liquid film saturates and covers the upper surface of the pad. The wafer to be polished floats upon the second liquid film within the pocket.

Confined water fixture for holding wafers undergoing chemical-mechanical

A SOI BiCMOS integrated circuit has CMOS devices formed in a thin epitaxial layer of 1,000 .ANG. and bipolar devices formed in a thick epitaxial layer of 1 .mu.m, the two thicknesses being formed by a process in which a set of oxide islands are formed on a first wafer; an epitaxial layer is grown from bipolar silicon regions up and over the islands in a step that forms the bottom portion of the bipolar regions; the first wafer is inverted and oxide-bonded to a second wafer with the newly grown epitaxial layer below the islands so that the new top surface has a high quality epitaxial layer; excess silicon is removed from the new surface and the surface is polished to a thickness of 1,000 .ANG. over the islands by use of a nitride polish stop layer, leaving a thick layer of epitaxial silicon of 1 .mu.m in the bipolar regions and a 1,000 .ANG. thick layer of epitaxial silicon in the CMOS regions.

Method of forming a BiCMOS SOI wafer having thin and thick SOI regions

The present invention is a self-aligned, vertical bipolar transistor structure and a method of manufacturing such a structure. Reducing lateral dimensions with optical lithography is difficult and not much is gained without concurrently reducing alignment tolerances. For bipolar transistors the alignment tolerance is particularly important since it determines the parasitic capacitances and resistances and thus directly affects speed. In this application a new fully self-aligned transistor structure is presented that self-aligns the shallow trench, extrinsic base contact, and the emitter polysilicon to the intrinsic device area. The structure has no critical alignments. To insure extrinsic-intrinsic base linkup the intrinsic base is put in early in the process, conserved during the stack etch, and patterned underneath the sidewall during the silicon mesa etch. Unlike other mesa-like transistor structures, no out-diffusion of the extrinsic-base is required and therefore low-temperature processing can be used to maintain a narrow vertical profile.

High performance vertical bipolar transistor structure via self-aligning

In the process of sidewall image transfer, a vertical step is etched in some material and then a conformal layer of some other material is deposited over the step. By reactive ion etching the conformal material can be anisotropically etched which results in a sidewall spacer of the second material on the vertical surfaces of the step material. By removing the step material, the free standing spacer can then be used as a mask. One area in which improvement is desired is in the selectivity of the etch of the spacer to the material immediately below it. Because of the limited number of materials and reactive ion etching gases it is difficult to avoid an etch in the underlying layer as the sidewall spacer is formed. A suitable etch stop is employed beneath the step material to avoid the problem. Because of the usual technology, the spacer material is plasma deposited silicon nitride and the step material is photoresist. Polysilicon, aluminum or similar metal is employed as an etch stop, since it is not by a CF.sub.4 based gas which is used to form the spacer.

Method of preventing asymmetric etching of lines in sub-micrometer range

This invention relates to a process for forming deep trenches in semiconductor substrates by Reactive Ion Etching and more particularly relates to an etching process which prevents lateral etching or 'blooming' in a heavily doped semiconductor region which is sandwiched by upper and lower lightly doped regions of semiconductor. Still more particularly it relates to an RIE process wherein the upper region is reactively ion etched in an atmosphere of CCl.sub.2 F.sub.2 and argon to at least a portion of the thickness of the upper region and wherein any remaining thickness of the upper region, the heavily doped region and at least a portion of the lower region are reactively ion etched in an atmosphere of CCl.sub.2 F.sub.2 and oxygen to provide a trench with uniform sidewalls.

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Salt Point, NY, United States of America

Ronald N Schulz