Amdahl Corporation

Ronald N Hilton

Jeffrey L Baker

Kent Wayne Wendorf

Nicholas Y Pang

Kham X Nguyen

Stephen C Magee

A storage unit for a data processing system includes a cache data buffer, a cache tag, and a translation lookaside buffer (TLB). Storage keys are maintained in the TLB with a separate valid bit, which allows a valid translation to be stored upon completion of a translation, even though the key is not yet available. With a valid translation in the TLB entry available, the requesting port is then able to send off a move in request to mainstore right away in parallel with a key request from the translator to the mainstore key array. In the typical case, the key will be returned several cycles ahead of the data, allowing it to be written into the TLB entry and validated in time for the move in data to be successfully bypassed to the requestor as soon as it arrives.

Computer system having cache memories with independently validated keys

An interface between a storage unit and a system control unit maintains a sequential processing when retrying linestores by providing a single piece of information that the linestore is a 'first' in a series. An initial request flag accompanies linestore requests to the system controller and is returned to the storage unit with linestore replies. A mode indicator coupled with the storage unit pipeline sets a retry mode latch in response to a linestore restart reply, and resets the retry mode latch in response to a linestore read reply by the system controller to an initial request. Logic in the pipeline suppresses requests for the system resource in the pipeline, other than initial requests, when the retry mode latch is set, such as by flagging data subject of the second flow as locked or otherwise invalid. The port includes a state machine which preserves the order of pending requests for the system resource.

Retry request system in a pipeline data processing system where each

A cache memory system includes a buffer having a plurality of segments storing lines of data in addressable storage locations. A first access path is used for accessing the plurality of segments in parallel for access by the CPU, and a second access path is provided for access to the plurality of segments in the buffer in parallel for cache consistency access. Access to damaged segments is selectively disabled by inhibiting tag match and line replacement through the first access path without affecting the second access path. Thus, by disabling the first access path to selected segments, a damaged segment is reconfigured offline without a quiescent state or an extended clocks off period affecting CPU performance.

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Cupertino, CA, United States of America

Ronald N Hilton