International Business Machines Corporation

Ronald M Smith

Phil C Yeh

Robert S DeBellis

Julian Thomas

Donald B Johnson

Stephen M Matyas

John D Wilkins

Lucina L Green

Timothy John Slegel

Eric M Schwarz

Charles Franklin Webb

Mark Anthony Check

John Stephen Liptay

Michael James Kelly

Michael F Cowlishaw

Dennis G Abraham

Richard J Schmalz

Peter H Gum

Randall J Easter

Vincent A Spano

Edward J D'Avignon

An Van Le

Werner Buchholz

Ronald Morton Smith, Sr

Casper A Scalzi

Shawn D Lundvall

Kenneth E Plambeck

Roger E Hough

Carl Edward Clark

Richard I Baum

Michael Gerard Mall

An V Le

Alan G Ganek

Phil Chi-Chung Yeh

Rostislaw Prymak

Donald W McCauley

John H Wilson

Patrick M Gannon

Susan B Stillman

Ramesh K Karne

Andrew R Heller

Terry L Borden

James Lum

Stephen J Schmandt

Arthur L Levin

Justin R Butwell

Margaret Croft Enichen

David S Wehrly

Rotislaw Prymak

Sandra L Rankin

Devon S Yu

A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.

Round for reround mode in a decimal floating point instruction

Detection of whether a result of a floating point operation is safe. Characteristics of the result are examined to determine whether the result is safe or potentially unsafe, as defined by the user. An instruction is provided to facilitate detection of safe or potentially unsafe results.

Detection of potential need to use a larger data format in performing floating point operations

A method and apparatus for decrypting an input block encrypted under a predetermined key in a cryptographic system having a cryptographic facility providing cryptographic functions for transforming blocks of data. The cryptographic functions include an encryption function for encrypting a block under a predetermined key and a transformation function for transforming a block encrypted under a first key to the same block encrypted under a second key. The cryptographic functions have at least one key pair with the property that successive encryption of a block under the keys of the pair regenerates the block in clear form. The input block is first transformed into an intermediate block encrypted under one of the key pair using the transformation function. The intermediate block is then further encrypted under the other of the key pair using the encryption function to generate an output block successively encrypted under the keys of pair, thereby to regenerate the input block in clear form. The invention is useful in cryptographic systems in which the decryption function being emulated by the transformation and encryption functions is unavailable for export control or other reasons.

Method and apparatus for performing strong encryption or decryption data using special encryption functions

Objects such as master keys or object protection keys that are kept in a protected environment of a crypto module are securely transferred between modules by means of transport keys. The transport keys are generated by public key procedures and are inaccessible outside the modules. Master keys are encrypted under the transport key within the protected environment of the source module, transmitted in encrypted form to the target module, and decrypted with the transport key within the protected environment of the target module. Object protection keys that are encrypted under a first master key kept in the protected environment of the source module are decrypted with the first master within the protected environment of the source module before being encrypted under the transport key. The object protection keys are encrypted under a second master key within the protected environment of the target module after being decrypted with the transport key. The procedure is secure since the transport key, the master keys and the object protection keys are never made available outside the protected environments of the crypto modules.

Method and apparatus for the secure transfer of objects between

The capabilities of a cryptographic module are controlled by a crypto configuration control (CCC) register that is initialized by one or more self-signed commands that are preformulated and signed with the digital signature key of the crypto module itself. The crypto module accepts a self-signed command only if the self-signature can be validated using the signature verification key of the module. In one implementation, the final configuration is determined by a single self-signed command. In another implementation, a first self-signed command is used to create an temporary configuration that allows one or more initialization authorities to issue additional commands fixing the final configuration. The self-signed commands are maintained separately from the crypto module and are distributed to the end user either physically or electronically. After the self-signed commands have been created and the secret exponent has been embedded in a particular crypto module, all copies of the secret exponent external to the crypto module are destroyed.

Method and apparatus for controlling the configuration of a

A computer processor floating point processor six cycle pipeline system where instruction text is fetched prior to the first cycle and decoded during the first cycle for the fetched particular instruction and the base (B) and index (X) register values are read for use in address generation. RXE Instructions are of the RX-type but extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine the exact format from the first 8 bits of the operation code alone. ESA/390 instructions SS, RR; RX; S; RRE; RI; and the new RXE instructions have a format which can be used for fixed point processing as well as floating point processing where instructions of the RXE format have their R1, X2, B2, and D2 fields in the identical positions in said instruction register as in the RX format to enable the processor to determine from the first 8 bits of the operation code alone that an instruction being decoded is an RXE format instruction and the register indexed extensions of the RXE format instruction, after which it gates the correct information to said X-B-D adder. During the second cycle the address add of B+X+Displacement is performed and sent to the cache processor's, and during the third and fourth cycles the cache is respectively accessed and data is returned, and during a fifth cycle execution of the fetched instruction occurs with the result putaway in a sixth cycle.

Address bit decoding for same adder circuitry for RXE instruction format

Pseudorandom numbers are generated in a cryptographic module in a cryptographically strong manner by combining a time-dependent value with a secret value and passing the result through a one-way hash function to generate a hash value from which a random number is generated. The secret value is continually updated whenever the cryptographic module is idle by a first feedback function that generates an updated secret value as a one-way function of the current secret value and the time-dependent value. In addition, the secret value is updated on the occurrence of a predetermined external event by a second feedback function that generates an updated secret value as a one-way function of the current secret value, the time-dependent value and an externally supplied value. Upon power-on reset, if the pseudorandom number generator has not been previously initialized, it initializes itself by resetting the time-dependent and secret values and requiring the second feedback function to perform a predetermined number of updates of the secret value in response to external events. Otherwise, the time-dependent and secret values are restored using values stored in backup registers. A hash of the current secret value that is different from either feedback function is used as a backup secret value to minimize the possibility that restoration will result in repetition of pseudorandom numbers.

Pseudorandom number generator with backup and restoration capability

A computer processor system having a floating point processor for instructions which are processed in a six cycle pipeline, in which prior to the first cycle of the pipeline an instruction text is fetched, and during the first cycle for the fetched particular instruction it is decoded and the base (B) and index (X) register values are read for use in address generation. Instructions of the RX-type are extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine from the first 8 bits of the operation code alone, the exact format of the instruction. Instructions formats include the ESA/390 instructions SS, RR; RX; S; RRE; RI: and the new RXE instructions. where instructions of the RXE format have their R.sub.1, X.sub.2, B.sub.2, and D.sub.2 fields in the identical positions in said instruction register as in the RX format to enable the processor to determine from the first 8 bits of the operation code alone that an instruction being decoded is an RXE format instruction and the register indexed extensions of the RXE format instruction, after which it gates the correct information to said X-B-D adder. During the second cycle the address add of B+X+Displacement is performed and sent to the cache processor's, and during the third and fourth cycles the cache is respectively accessed and data is returned, and during a fifth cycle execution of the fetched instruction occurs with the result putaway in a sixth cycle.RXE instructions can be used for floating point processing and fixed point processing.

Computer processor system for executing RXE format floating point

Pseudorandom numbers are generated in a cryptographic module in a cryptographically strong manner by combining a time-dependent value with a secret value and passing the result through a one-way hash function to generate a hash value from which a random number is generated. The secret value is continually updated whenever the cryptographic module is idle by a first feedback function that generates an updated secret value as a one-way function of the current secret value and the time-dependent value. In addition, the secret value is updated on the occurrence of a predetermined external event by a second feedback function that generates an updated secret value as a one-way function of the current secret value, the time-dependent value and an externally supplied value. Upon power-on reset, if the pseudorandom number generator has not been previously initialized, it initializes itself by resetting the time-dependent and secret values and requiring the second feedback function to perform a predetermined number of updates of the secret value in response to external events. Otherwise, the time-dependent and secret values are restored using values stored in backup registers. Special test modes that cannot be activated during normal operation make the output of the pseudorandom number generator deterministic, but use the same registers, one-way functions, and data paths as the normal mode.

Pseudorandom number generator with normal and test modes of operation

Pseudorandom number generator

A new Test FP Data Class operation is provided which utilizes a 12-bit mask to determine to which of the 12 possible data classes a floating point number belongs and sets a condition code accordingly. As preferably embodied, a typical IBM System 390 instruction format is adapted to implement a Test FP Data Class operation. The class and sign of the first operand are examined to select one bit from the second-operand address. A condition code of 0 or 1 is set according to whether the selected bit is 0 or 1. The second-operand address is not used to address data; instead, individual bits of the address are used to specify the applicable combinations of operand calls and sign.

Method and apparatus for determining floating point data class

A system and method for dispatching logical central processing units (CPUs) among physical CPUs in a multiprocessor computer system having multiple logical partitions, wherein the cryptographic facilities may not be interchangeable. According to the present invention, the logical CPUs are dispatched among the physical CPUs according to either an affinity, floating, or disabled scheduling method. The affinity scheduling method is used when the crypto facilities are not interchangeable or when non-interchangeable crypto functions are performed. The floating scheduling method is used when the cryptographic facilities are interchangeable and interchangeable crypto functions are performed. The disabled scheduling method is used when the logical CPU is not authorized to issue cryptographic instructions.

Scheduling normally interchangeable facilities in multiprocessor

Asynchronously transfers blocks of data (called pages) between two different electronic media of a data processing system. The different media may be a system main storage and a system expanded storage or a non-volatile external type of storage, either of which use different addressing than the main storage. All of these storages may be made of DRAM or SRAM technology with battery backup when necessary. The invention splits the involvement of a program requesting a page transfer into a pair of instructions per page transfer executing on one or more central processors. The first instruction of a pair starts another processor that controls the asynchronous page transfer, and the second instruction of the pair enables the communication of the end of the page transfer to the program. Neither instruction in the pair interrupts the program for the page transfer. A processor executing the starting instruction is immediately free to execute any other available instructions. Although both instructions in a pair may be executed by one processor, the pair may be executed by separate processors. And the execution of other instructions may overlap the page transfer between the execution of the pair.

Execution of page data transfer by PT processors and issuing of split

A cryptographic facility implements a multiple key part import procedure. The installation manager can verify that a key part has been correctly entered and has not been compromised. The security requirement for the procedure is that no single party can subvert the system security by misusing the procedure. This is accomplished by the use of a control-vector-dependent verification pattern to indicate that each key part has been accepted by using the proper control vector and the use of different key switch positions to specify whether the key part is a master key part or an operational key part and whether the key part is a first part or a subsequent key part. The apparatus provides an automatic reset of the key part register at the completion of each key-entry instruction so that each key part can be imported only once. This prevents the same key part from being imported twice as different key part types. The apparatus also prevents a key part from being combined with itself to create a known key. The procedure is fail-safe so that the program cannot steal a key part from a previously failed procedure.

Method and apparatus for validating entry of cryptographic keys

A working key of a certain key type is to be transmitted from a first system (having a first usage-control value associated with keys of the certain type) and a second system (having a second usage-control value associated with keys of the certain type). A translation control value, associated with the certain key type, is generated, functionally relating the first and second usage-control values. The translation control value is used in a cryptographic function to send or receive the working key between systems, the cryptographic function being designed to produce valid results when the correct translation control value, and usage-control values, are employed, and unpredictable results otherwise. Effectively, the first usage-control value is translated to the second usage-control value.

Secure translation of usage-control values for cryptographic keys

Growing community of inventors

Wappingers Falls, NY, United States of America

Ronald M Smith